EDA技術與Verilog HDL（英文版）

內容簡介

《EDA 技術與 Verilog HDL （英文版）》 systematically introduces EDA technology and Verilog HDL. It well combines the basicknowledge, programming skills and practical methods of EDA technology and Verilog HDL with the actualengineering development technologies. According to the regulations and requirements of the classroom teachingand experimental operation in universities and colleges, and with the aim of enhancing the practical engineeringdesign ability and independent innovation capability of students, the authors reasonably arrange the content of thewhole book. The book is divided into seven parts: overview of EDA technology, syntax knowledge and practicaltechnology of Verilog HDL, detailed usage of Quartus and IP module, design technology of finite state machine,16/32-bit practical CPU design technology and innovative practical project, ModelSim-based Test Benchsimulation technology and a large number of practical system design examples. Apart from a few chapters andsections, most of the chapters arrange the corresponding exercises and a large number of highly targetedexperiments and design projects. All of the Verilog HDL examples enumerated in the book have passed throughthe compiling or hardware testing.

《EDA 技術與 Verilog HDL （英文版）》 can be used as the textbook or reference book for the subjects of electronics, computer, andautomation, and can provide teaching PPT courseware, experimental source programs and demonstration videosand so on.

圖書目錄

Chapter 1 Introduction 1

1.1 EDA Technology 1

1.2 Object for EDA Technology 3

1.3 Common Hardware Description Languages 5

1.4 Advantages of EDA Technology 7

1.5 Development Flow for FPGA and CPLD 9

1.5.1 Design Input 9

1.5.2 Synthesis 10

1.5.3 Fit (Place and Route) 13

1.5.4 Simulation 13

1.5.5 RTL Description 14

1.6 Programmable Logic Devices 14

1.6.1 Classification of PLD 15

1.6.2 Programming Principle of PROM 16

1.6.3 GAL 18

1.7 Structure and Programming Principle of CPLD 20

1.8 Structure and Working Principle of FPGA 23

1.8.1 Logical Structure of LUT 23

1.8.2 Structural Principle of Cyclone 4E Series Devices 24

1.8.3 FPGA Device with Embedded Flash 27

1.8.4 Major Manufacturers of FPGA 27

1.9 Hardware Testing Technology 28

1.9.1 Internal Logic Test 28

1.9.2 JTAG Boundary Scan Test 28

1.10 Programming and Configuration 29

1.11 Quartus 30

1.12 IP Core 32

1.13 Major EDA Software Companies 33

1.14 Development Trend of EDA 34

Exercises 36

Chapter 2 Program Structure and Data Type 37

2.1 Verilog Program Structure 37

2.1.1 Expression of Verilog Module 38

2.1.2 Signal Name and Mode of Verilog Module Port 39

2.1.3 Definition of Verilog Signal Type 40

2.1.4 Function Description of Verilog Module 41

2.2 Data Types of Verilog 41

2.2.1 Net Type 41

2.2.2 Definition of Wire Type Variable 41

2.2.3 Register Type 42

2.2.4 Definition of Register Type Variable 42

2.2.5 Definition of Integer Type Variable 43

2.2.6 Memory Type 44

2.3 Verilog Syntax Rules 45

2.3.1 Four Logical States in Verilog 46

2.3.2 Digital Expression Forms of Verilog 46

2.3.3 Expression of Data Type 47

2.3.4 Constant 47

2.3.5 Identifiers, Keywords, and Other Syntax Rules 49

2.3.6 Usage of parameter and localparam 51

Exercises 51

Chapter 3 Behavioral Statements 53

3.1 Procedural Statement 53

3.1.1 always Statement 54

3.1.2 The Application of always Statement in D flip-flop Design 55

3.1.3 The Application of Multi-Process and Asynchronous Sequential Circuit

Design 56

3.1.4 Verilog Expression of Simple Up Counter 57

3.1.5 initial Statement 58

3.2 Block Statement 60

3.3 case Conditional Statement 61

3.4 if Conditional Statement 62

3.4.1 General Expression of if Statement 62

3.4.2 Combinational Circuit Design Based on if Statement 63

3.4.3 Sequential Circuit Design Based on if Statement 65

3.4.4 Design of DFF with Asynchronous Reset and Clock Enable 67

3.4.5 Design of DFF with Synchronous Reset 68

3.4.6 Design of Latches with Clear 69

3.4.7 Characteristics and Rules of Clock Procedural Statement 70

3.4.8 Practical Up Counter Design 72

3.4.9 Shift Register Design with Synchronized Preset Function 74

3.4.10 Conditional Instructions in if Statements 76

3.5 Statement of Procedural Assignment 77

3.6 Loop Statement 78

3.6.1 for Statement 78

3.6.2 while Statement 79

3.6.3 repeat Statement 81

3.6.4 forever Statement 81

3.7 task and function Statements 81

Exercises 84

Chapter 4 FPGA Hardware Implementation 86

4.1 Code Editing Input and System Compilation 86

4.1.1 Design File Edit and Input 86

4.1.2 Creating a Project 87

4.1.3 Constraint Item Setting 89

4.1.4 Comprehensive Synthesis and Compilation 90

4.1.5 Application of RTL Viewer 92

4.2 Timing Simulation 93

4.3 Hardware Testing 96

4.3.1 Pin Assignment 97

4.3.2 Compiled File Download 99

4.3.3 Indirect Programming of Configuration Chip through JTAG 100

4.3.4 USB-Blaster Driver Installation 102

4.4 Circuit Schematic Design Flow 102

4.4.1 Half-adder Design 102

4.4.2 Top-level Design of Full-adder 104

4.4.3 Timing Simulation and Hardware Testing of Full Adders 105

4.5 Pin Assignment Using Attributes 107

4.6 Usage of SignalTap II 108

4.7 Trigger Signal Edit of SignalTap II 114

4.8 Installation of Quartus II 13.1 114

Exercises 119

Labs and Designs 120

Lab 4-1 Multiplexer Design 120

Lab 4-2 Hexadecimal 7-segment Digital Display Decoder Design 120

Lab 4-3 8-bit Hardware Multiplier Design 122

Lab 4-4 Design of a Digital Frequency Meter Using Macro Modules 122

Lab 4-5 Counter Design 127

Lab 4-6 Digital Scan and Display Circuit Design 128

Lab 4-7 Half-integer and Odd Frequency Divider Design 128

Chapter 5 Operators and Structural Description Statement 131

5.1 Operators of Operation 131

5.1.1 Bit Logical Operator 131

5.1.2 Logical Operator 132

5.1.3 Arithmetical Operator 132

5.1.4 Relational Operator 134

5.1.5 Example of Adder based on BCD Code 135

5.1.6 Contraction Operator 136

5.1.7 Parallel Connection Operator 136

5.1.8 Shift Operator 137

5.1.9 Example of Shift Operator 137

5.1.10 Conditional Operator 138

5.2 Continuous Assignment Statement 139

5.3 Instantiation Statement 140

5.3.1 Half-adder Design 140

5.3.2 Full-adder Design 141

5.3.3 Verilog Instantiation Statement and Its Usage 142

5.4 Application of Parameter Transmission Statement 144

5.5 Structural Description with Library Component 145

5.6 Compiling Directive Statement 147

5.6.1 Macro Definition Statement 147

5.6.2 File Inclusive Statement, 'include 148

5.6.3 Conditional Compilation Statement, 'ifdef, 'else, 'endif 149

5.7 Application of Attribute of Keep 150

5.8 Usage of SingalProbe 152

Exercises 154

Labs and Designs 157

Lab 5-1 High-speed Hardware Divider Design 157

Lab 5-2 Design of Various Types of Shift Registers 158

Lab 5-3 Verilog Code-based Frequency Meter Design 158

Lab 5-4 8-bit Adder Design 159

Lab 5-5 VGA Displayer Control Circuit Design 160

Chapter 6 The Usage of LPM Macro Module 165

6.1 The Example of Invoking Macro Module of Counter 165

6.1.1 The Invoking of the Text Code of the Counter LPM Module 165

6.1.2 Application of LPM Counter Code and Parameter Transmission Statement . 167

6.1.3 Project Creation and Simulation Testing 169

6.2 Example of Building Attribute Control Multiplier 169

6.3 Usage of Macro Block of LPM_RAM 171

6.3.1 Initialization File and Its Generation 172

6.3.2 Invoking LPM_RAM by Schematic Diagram Method 174

6.3.3 Test LPM_RAM 176

6.3.4 Expression of Memory Initialization File Loading of Verilog Code Description . 177

6.3.5 Structure Control of Memory Design 178

6.4 Usage Examples of LPM_ROM 180

6.4.1 Design of Simple Sinusoidal Signal Generator . 180

6.4.2 Hardware Implementation and Testing of Sinusoidal Signal Generator . 182

6.5 Application of In-System Memory Content Editor 183

6.6 Invoke of Embedded PLL of LPM 185

6.6.1 Building Embedded PLL Component 185

6.6.2 PLL Test . 188

6.7 The Usage of In-System Sources and Probes Editor 188

6.8 Principle and Application of DDS 191

6.8.1 Principle of DDS 192

6.8.2 Example of DDS Signal Generator 194

Exercises 195

Labs and Designs 196

Lab 6-1 Look-up Table based Hardware Operator Design 196

Lab 6-2 Sinusoidal Signal Generator Design 197

Lab 6-3 Design of Simple Data Acquisition System 197

Lab 6-4 DDS-based Sinusoidal Signal Generator Design 198

Lab 6-5 Phase-shifted Signal Generator Design 199

Lab 6-6 Amplitude-Modulated Signal Generator Design 200

Lab 6-7 Hardware-Based De-jitter Circuit Design 200

Chapter 7 Deep Understanding of Verilog HDL 203

7.1 Two Types of Assignment Statements in Process 203

7.1.1 Blocking Assignment with Unspecified Time-delay 203

7.1.2 Blocking Assignment with Specified Time-delay 204

7.1.3 Non-blocking Assignment with Unspecified Time-delay 205

7.1.4 Non-blocking Assignment with Specified Time-delay 207

7.1.5 Deep Understanding of the Features of Blocking and Non-blocking

Assignments 209

7.1.6 Further Discussion of Different Initialization Ways 211

7.2 Discussion of Procedural Statement 213

7.2.1 Conclusion of Procedural Statement Application 213

7.2.2 Relationship between Incomplete Conditional Statement and Sequential

Circuit 214

7.3 Design of Three-state and Bidirectional Port 217

7.3.1 Design of Three-state Control Circuit 217

7.3.2 Design of Bidirectional Port . 217

7.3.3 Design of Three-state Bus Control Circuit 220

7.4 Resource Optimization 222

7.4.1 Resource Sharing 223

7.4.2 Logic Optimization 224

7.4.3 Serialization 225

7.5 Speed Optimization 226

Exercises 229

Labs and Designs 230

Lab 7-1 Design of the Signal Detection Circuit of 4×4 Array Keyboard 230

Lab 7-2 Design of Direct Current Motor-based Synthesized Measurement and

Control System 232

Lab 7-3 Design of Control Module of VGA-based Simple Image Displaying 234

Lab 7-4 Design of Hardware-based Music Performing Circuit 235

Lab 7-5 Design of Electronic Organ Circuit based on PS2 Keyboard Control

Model 240

Chapter 8 Design Technology of State Machine 243

8.1 General Form of Verilog State Machine 243

8.1.1 Characteristics and Advantages of State Machine 243

8.1.2 General Structure of State Machine 245

8.1.3 Initial Control and Expression 249

8.2 Moore-type State Machine 250

8.2.1 State Machine with Multiprocess Structure 251

8.2.2 Sequence Detector and Its State Machine Design 255

8.3 Mealy-type State Machine 257

8.4 State Machine with Different Coding Types 260

8.4.1 Direct Output Coding 260

8.4.2 Defining the State Coding with the Use of Macro Definition Statement 262

8.4.3 Sequential Coding 263

8.4.4 One-hot Coding 264

8.4.5 Setting of State Coding 265

8.5 Design of Safe State Machine 266

8.5.1 State Guiding Method 267

8.5.2 Monitoring Method of State Coding 268

8.5.3 Auto-generation of Safe State Machine with the Use of EDA Tool 269

Exercises 269

Labs and Designs 270

Lab 8-1 Design of Sequence Detector 270

Lab 8-2 Design of ADC Sampling Control Circuit 270

Lab 8-3 Design of Intelligent and Logical Pen with Five Functions 272

Lab 8-4 Design of Data Acquisition Module 274

Chapter 9 16/32-bit CPU Innovation Design 276

9.1 Architecture and Characteristics of KX9016 276

9.2 Design of KX9016 Basic Hardware System 280

9.2.1 Module of One-step Beat Generation 280

9.2.2 ALU Module 281

9.2.3 Comparator Module 281

9.2.4 Basic Register and Register Array 282

9.2.5 Shifting Register Module 286

9.2.6 Program and Data Memory Module 286

9.3 Design of KX9016v1 Instruction System 287

9.3.1 Instruction Format 287

9.3.2 Instruction Operation Code 289

9.3.3 Example of Software Program Design 290

9.3.4 Design of KX9016 Controller 292

9.3.5 Example of Instruction Design 297

9.4 Timing Simulation and Hardware Testing of KX9016 298

9.4.1 Timing Simulation and Waveform Analysis of Instruction Execution 299

9.4.2 Hardware Testing of CPU Operation Condition 301

9.5 Examples of Application Program Design and System Optimization of KX9016 304

9.5.1 Multiplication Algorithm and Its Hardware Implementation 304

9.5.2 Division Algorithm and Its Hardware Implementation 306

9.5.3 Optimization of KX9016v1 Hardware System 307

9.6 Design of 32-bit RISC-V Processor 309

9.6.1 RISC-V Basic Structure and Basic Integer Instruction Set RV32I 309

9.6.2 2-bit Multiplication Instruction Set RV32M 312

9.6.3 16-bit Compressed Instruction Set RVC 313

Exercises 314

Labs and Designs 314

Lab 9-1 Comprehensive Experiment of 16-bit CPU Design 314

Lab 9-2 Experiment of New Instruction Design and Program Testing 315

Lab 9-3 Optimization Design and Innovation of 16-bit CPU . 316

Chapter 10 Verilog HDL Simulation 318

10.1 Verilog HDL Simulation Flow 319

10.2 Example of Verilog Test Bench 322

10.3 Testing Flow of Verilog Test Bench 324

10.4 Verilog System Tasks and System Functions 327

10.4.1 System Tasks and System Functions 327

10.4.2 Precompiled Statements 333

10.5 Delay Model 334

10.5.1 # Delay and Gate Delay 334

10.5.2 Delay Description Block 335

10.6 Other Simulation Statements 335

10.6.1 fork-join Block Statements 336

10.6.2 wait Statement 337

10.6.3 force, release Statement 337

10.6.4 deassign Statement 338

10.7 Generation of Simulation Excitation Signals 338

10.8 Digital System Simulation 339

Exercises 340

Labs and Designs 341

Lab 10-1 Simulating the Test Bench of Counter on ModelSim 341

Lab 10-2 Design and Simulate a 16-Bit accumulator on ModelSim 341

Appendix A Development Systems and Softwares for EDA 342

A.1 KX-CDS Series EDA/SOPC System 343

A.1.1 Modular Independent Innovation Experimental Design Structure . 344

A.1.2 Multifunctional Reconfigurable High-Efficiency Experimental Control

System 345

A.1.3 FPGA Core Board of Different Functional Types 345

A.2 Some Expansion Modules for Experiments 348

A.3 Usage of MIF file generator 350

A.4 Reference Table for Extending Core Board FPGA to KX-CDS System 352

A.5 Part of the Experimental Circuit Diagram with Switchable Multifunctional

Reconfigurable Structure 354

A.6 HX1006A and Pin Assignment Tool 357

References 359

EDA技術與Verilog HDL（英文版）

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