黃科傑

黃科傑

黃科傑，於2003年和2006年在浙江大學信息與電子工程學院先後獲得本科學位和碩士學位，2014年在新加坡國立大學電子與計算機工程系獲得博士學位。現任教於浙江大學信息與電子工程學院。

基本介紹

  • 中文名：黃科傑
  • 畢業院校：浙江大學
  • 學位/學歷：博士
  • 專業方向：神經形態晶片、深度學習加速器、非易失性邏輯電路等
  • 職務：博士生導師
個人簡歷,專利成果,中國專利,Granted Patents,Patent Application,Provisional,教學工作,研究內容,發表論文,Journal,Conference,Book Chapter,

個人簡歷

黃科傑博士於2003年和2006年在浙江大學信息與電子工程學院先後獲得本科學位和碩士學位，2014年在新加坡國立大學電子與計算機工程系獲得博士學位。從2006年開始從事積體電路設計，先後入職於三星半導體公司（Samsung Semiconductor），上海格科微電子（GalaxyCore），賽靈思新加坡分公司（Xilinx），新加坡新加坡科技研究局（A*STAR），新加坡科技設計大學（SUTD）。2016年10月以“百人計畫”研究員的身份加入浙江大學信息與電子工程學院。黃科傑博士主要從事基於新型阻值存儲器的低功耗電路與系統的開發，深度學習與硬體加速環境的開發，以及神經形態計算晶片設計與開發。他目前已經在本領域頂級期刊如IEEE TCAS-I, IEEE TCAS-II，IEEE TVLSI，Advanced Material, EDL, SMALL和著名國際會議如NANOARCH，IJCNN,NVMTS發表高水平學術論文30餘篇，獲得美國專利4項，美國專利申請3項。同時他是IEEE高級會員，並擔任IEEE Access, TCAS，TVLSI，EDL等多個國際期刊的審稿人。

專利成果

中國專利

黃科傑、肖蕊、沈海斌，一種基於radix-4編碼和差分權重存儲的乘累加電路,2019104623748,2019-05-30
黃科傑、潘雲潔、沈海斌，基於權重分布的卷積神經網路低位寬量化方法,2019104636786,2019-05-30
黃科傑、周璇、朱曉雷，一種基於racetrack memory的乘法器及其操作方法,2019104359853,2019-05-23
黃科傑、曹家駿、沈海斌，一種基於RRAM的非易失性8位Booth乘法器,2019104814374,2019-06-04
黃科傑、朱超陽、沈海斌，一種基於結構化剪枝和低比特量化的神經網路處理器,201910609993.5,2019-07-08
黃科傑、張賽、沈海斌，一種基於多位並行二進制突觸陣列的神經形態計算電路,201910609991.6,2019-07-08

Granted Patents

  1. Foong Huey Chian,Huang Kejie. 'Write control circuits and write control methods'. US Patent. US9,257,177, 2016.
  2. Huang Kejie. 'A circuit arrangement and a method of writing states to a memory cell'. US Patent, US8942024, 2015.
  3. Lua Yan Hwee Sunny,Huang Kejie. 'Writing circuit for a magnetoresistive memory cell, memory cell arrangement and method of writing into a magnetoresistive memory cell of a memory cell arrangement'. US Patent. US8,773,897, 2014.
  4. Huang Kejie, Ning Ning. 'Reading Circuit for A Resistive Memory Cell'. US Patent. US8,867,260, 2014. SG Patent Application, SG/201303132-3, 13/03/2013.

Patent Application

  1. Huang Kejie, Foong Huey Chian. 'Latch Circuit and Data Processing System'. US Patent Application. US/14/092,975, 11/28/2013.
  2. Huang Kejie, Sunny Lua Yan Hwee, Arthur Ang. 'A Current Writing Circuit For A Resistive Memory Cell Arrangement'. US/SG Patent Application. US20120300531, 2012. SG/201203494-8, 23/05/2012.
  3. Huang Kejie, Zhao Rong. 'Writing Circuit for A Resistive Memory Cell Arrangement and A Memory Cell Arrangement'. US/SG Patent Application. US20130077383, 2013. SG/201106907-7, 9/23/2011.

Provisional

  1. Huang Kejie, Tan Theng Kiat. 'An Optimised Scheme to Minimise Resistance Drift for Multi-Level Phase Change Memory Array'. US/61/731,005, 11/29/2012.
  2. Huang Kejie. 'A New Reference Cell Circuit for current writing STT-MRAM to Reduce the Cell Resistance Distribution'. US/61/567,163, 06/12/2011.
  3. Huang Kejie, Lua Yan Hwee Sunny. 'A Compact Read-Write Circuit for Bi-Directional Current Writing STT-MRAM'. US/61/568,688, 09/12/2011.

教學工作

現開設課程：
2019春夏 計算機組成與系統結構
現參與授課：
2017-2018 電子科學與技術學科前沿
曾參與開課情況：
2017 ‘Introduction of Computing’ at ZJU-UIUC
2015 ‘Design and Fabrication of MEMS’ at SUTD
2015 ‘Digital Integrated Circuits Design’ at SUTD

研究內容

1. 片上深度學習
使嵌入式系統、穿戴設備、物聯網具備人工智慧的能力是萬物智慧型的基礎。但是目前在嵌入式環境中實現深度學習的最大的挑戰是網路規模過大與設備計算能力不足之間的矛盾。我們正在開發面向片上的深度學習晶片，主要分以下三個方向：1. 通過模型壓縮與最佳化，如模組化循環矩陣，FFT 快速運算，指數域量化，剪枝，預測等方法，來大幅度減少深度學習網路的參數與計算複雜度，提高晶片的計算能力。2. 為了提高晶片的利用率和通用性，研究局部可重構技術、專用指令集以及以及編譯器。3. 使用全新存儲器、處理器架構和編譯器來實現無主存深度學習處理器。4. 軟硬體協同最佳化，全新AI晶片設計流程，從“晶片-編譯器-軟體”向“編譯器-軟體-晶片”轉變，實現快速自動生成AI晶片的開發平台。
2. 非易失神經形態晶片
神經形態晶片以一種更加類腦的方式來實現神經網路運算。非易失性神經形態晶片將使用非易失性存儲器，如憶阻器，來大幅度提升晶片的密度，實現零待機功耗。神經形態晶片的研究也主要分為三個方向：1. 基於憶阻器的存儲器內計算的方法，來徹底解決傳統處理器上最大的瓶頸 -存儲器與計算單元分離的問題。研究基於憶阻器的神經元電路、晶片架構、訓練算法和電路實現。2. 使用可重構的方法來開發通用的架構，既實現高速並行運算，也滿足不同的網路結構與規模的要求，提升晶片利用率。3. 神經網路與晶片架構之間的映射算法與最佳化。
3. 非易失計算系統
CMOS 工藝的縮放使現有晶片系統面臨了新的挑戰，如指數型上升的漏電流和互連線上的動態功耗。我們在研究使用新的阻值非易失性存儲器來解決上述的問題，同時實現零待機功耗。目前已經提出了多種設計方案，如非易失性暫存器，非易失性乘法器，本地化非易失存儲陣列，非易失可重構電路等，大幅度減少了記憶體讀寫功耗，以及漏電功耗。
4. 智慧型安全
隨著信息技術的飛速發展，傳統的加密與安全管理技術面臨了越來越多的挑戰。由於生物特徵的唯一性，可以很好的用來進行身份認證。傳統的指紋識別由於被合成出通用性指紋，亦面臨的信息安全的問題，所以需要利用新的技術和生物特徵來加強安全性。我們目前正在研究使用人臉、心電信號或者步伐姿態來進行身份認證。在身份認證中，我們提出了全新信號提取、活體識別的方法來大幅度提升認證的準確率並有效的防止電子欺騙。

發表論文

Journal

2019
23. Ruizhen Wang, Kejie Huang*, Haibin Shen, Feng Xiao. 'Hybrid iris center localization method using cascaded regression, weighted averaging, and weighted snakuscule'. Optical Engineering, 2019.
22. Yifan Chu, Haibin Shen, Kejie Huang*. 'ECG Authentication Method Based on Parallel Multi-scale One-dimensional Residual Network with Center and Margin Loss'. IEEE Access, pp. 51598-51607, 23 April 2019. [DOI]
2018
21.Yishu Zhang; Wei He; Yujie Wu; Kejie Huang; Yangshu Shen; Jiasheng Su; Yaoyuan Wang; ZiyangZhang; Xinglong Ji; Guoqi Li; Hongtao Zhang; Sen Song; Huanglong Li; Litao Sun; Rong Zhao;Luping Shi. 'Highly Compact Artificial Memristive Neuron with Low Energy Consumption'.Small.14 (51), 1802188,14 November 2018. [DOI]
20.Feng Xiao, Dandan Zheng,Kejie Huang, Yue Qiu, Haibin Shen. 'An Accurate Regression-based Gaze Tracking System with ASingle Camera'.Journal of EyeMovement Research (JEMR), 11 (4), 2018. [PDF]
19.Feng Xiao, Kejie Huang*, Yue Qiu, Haibin Shen. 'Accurate Gaze Estimation based on Average Binary-Connected-Component-Centroid'. Electronics Letters (EL),vol. 54, no. 17, pp.1026- 1028, 8/23/2018. [DOI]
18. Yue Qiu, Kejie Huang*, Feng Xiao, Haibin Shen. 'A Segment-Wise Reconstruction Method Based on Bidirectional Long Short Term Memory for Power Line Interference Suppression'.Biocybeetics and Biomedical Engineering (BBE), vol. 38, no. 2, pp. 217-227, 2018. [PDF]
17. Feng Xiao,Kejie Huang*,Yue Qiu, Haibin Shen.'Accurate Iris Center Localization Method Using Facial Landmark, Snakuscule, Circle Fitting and Binary Connected Component'.Multimedia Tools and Applications(MTAP), Volume 77, Issue 19,pp. 25333–25353,October 2018
16.Kejie Huang, Rong Zhao, Yong Lian. 'Racetrack Memory based Low Power and High Density Non-volatile Look-Up Table (LUT)'.Elsevier Journal of Parallel and Distributed Computing(JPDC), Volumn 117 Pages 127–137, July 2018.
15.Xinglong Ji, Li Song, Wei He, Kejie Huang, Zhiyuan Yan, Shuai Zhong, Yishu Zhang and Rong Zhao*. 'A Super Nonlinear Electrodeposition-diffusion-controlled Thin Film Selector'.ACS Applied Materials & Interfaces(AMI). vol.28, no. 10(12), pp. 10165-10172. 2018 Mar 15. [DOI]
14.Kejie Huang, Wei He, Rong Zhao. 'A Two-Step Sensing Circuit for the Hysteresis Loop Selector based Resistive Non-Volatile Memory Arrays'.IEEE Trans. on Circuits and Systems II: Express Briefs(TCASII),vol. 65, no. 1, pp. 101--105, Jan 2018.
2017
13. Wei He, Hongxin Yang, Li Song, Kejie Huang, Rong Zhao. 'A Novel Operation Scheme Enabling Easy Integration of Selector and Memory'. IEEE Electronics Device Letter (EDL). Vol. 38, no. 2, pp. 172 - 174, Feb. 2017.[PDF ]
12. Changhong Wang; Wei He; Yi Tong; Yishu Zhang; Kejie Huang; Li Song; Shuai Zhong;Rajasekaran Ganeshkumar. 'Memristive Devices with Highly Repeatable Analog States Boostedby Graphene Quantum Dots'. Small, 13(20),15 March 2017. (DOI)
2016
11.Kejie Huang, Rong Zhao. 'Magnetic Domain-Wall Racetrack Memory based Non-volatile Logic for Low Power Computing and Fast Run-Time-Reconfiguration'. IEEE Trans. on VLSI systems (TVLSI), vol. 24, no. 9, pp. 2861-2872, 2016.[PDF ]
10.Kejie Huang, Rong Zhao, Wei He, Yong Lian. 'High Density and High Reliability Non-volatile Field Programmable Gate Array (FPGA) with Staked 1D2R RRAM Array'.IEEE Trans. Very Large Scale Integration (VLSI) Systems(TVLSI), vol. 24, no. 1, pp. 139-150, 2016.[PDF ]
9.Kejie Huang, Rong Zhao, Yong Lian. 'Racetrack Memory based Non-volatile Storage Elements for Multi-context FPGAs'.IEEE Trans. on VLSI systems(TVLSI), vol. 24, no. 5, pp. 1885-1984, 2016.[PDF ]
2015
8. Kejie Huang, Rong Zhao, Yong Lian. 'A Low Power and High Sensing Margin Non-volatile Full Adder Using Racetrack Memory'. IEEE Trans. on Circuits and Systems I: Regular Paper (TCASI), vol. 62, no. 4, pp.1109-1116, Apr. 2015.[PDF ]
7. Ning Ning, Guoqi Li, Wei He, Kejie Huang, Li Pan, Kiruthika Ramanathan, Rong Zhao,Luping Shi. 'Modeling Neuromorphic Persistent Firing Networks'. International Journal ofIntelligence Science, vol. 5, pp. 89-101, 2015.[PDF ]
2014
6. Kejie Huang, Yajun Ha, Rong Zhao, Akash Kumar, Yong Lian. 'A Low Active Leakage and High Reliability Phase Change Memory (PCM) based Non-Volatile FPGA Storage Element'. IEEE Trans. Circuits and Systems I: Regular Paper (TCASI), vol.61, no.9, pp.2605-2613, Sep. 2014.[PDF]
5. Kejie Huang, Rong Zhao, Ning Ning, Yong Lian. 'A Low Power Localized 2T1R STT-MRAM Array with Pipelined Quad Phase Saving Scheme for Zero Sleep Power Systems'. IEEE Trans. Circuits and Systems I: Regular Paper (TCASI), vol.61, no.9, pp.2514-1623, Sep. 2014.[PDF ]
4. Kejie Huang, Ning Ning, Yong Lian. 'Optimization Scheme to Minimize Reference Resistance Distribution of Spin-transfer-torque MRAM'. IEEE Trans. Very Large Scale Integration (VLSI) Systems (TVLSI), vol.22, no.5, pp.1179-1182, May 2014.[PDF]
3. Wei He^, Kejie Huang^, et al. Enabling an Integrated Rate-temporal Learning Scheme on Memristor. Scientific Reports (SR) 4. ^Equal contribution.[PDF ]
2. Tae Hoon Lee, Desmond Loke, Kejie Huang, Wei-Jie Wang, Stephen R. Elliott. 'Tailoring Transient-amorphous States: Towards Fast and Power-efficient Phase-change Memories and Neuromorphic Computing'. Advanced Materials (AM), vol. 26, no. 44, pp. 7493-7498.[PDF]
2013
1. Kejie Huang, Yong Lian. 'A Low Power Low Vdd Non-volatile Flip-flop using STT-MRAM'.IEEE Trans. on Nanotechnology (TNANO), vol.12, no.6, pp.1094-1103, Nov. 2013.[PDF]

　　

Conference

2019
8. Kejie Huang, Chuyun Qin, 'eNVM Based In-memory Computing for Intelligent and Secure Computing Systems',In 32th International System-On-Chip Conference (SOCC), 3-6 Sep, 2019.
7. Kejie Huang,'A Two-Step Sensing Circuit for the Hysteresis Loop Selector based Resistive Non-Volatile Memory Arrays',In52th International Symposium on Circuits and Systems(ISCAS), 26-29 May, 2019.
2017
6. Kejie Huang, Rong Zhao. 'Domain-Wall Racetrack Memory for In-Memory Computing'. In50th International Symposium on Circuits and Systems(ISCAS), 28-31 May, 2017.
5. Yue Qiu, Kejie Huang*, Feng Xiao, Haibin Shen. 'Power-Line Interference Suppression inElectrocardiogram using Recurrent Neural Networks'. The 10th International Congress on Imageand Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI), 14-16 Oct, 2017.
2014
4.Kejie Huang, Rong Zhao. 'Low Power Computing Using Resistive Non-volatile Memories'. In 14th Non-volatile Memory Technology Symposium (NVMTS), 27-29 October, 2014.[PDF]
3.Kejie Huang, Rong Zhao, Yong Lian. 'STT-MRAM based Low Power Synchronous non-volatile Logic with Timing Demultiplexing'. In 10th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH), 8-10 July, 2014.[PDF ]
2012
2. Ning Ning, Kejie Huang, Luping Shi. 'Articial Neuron with Somatic and Axonal Computation Units: Axon as a Slow Leaky Integrator Complementry to the fast somatic integration'. In2012 International Joint Conference on Neural Networks (IJCNN), 10-15 June, 2012.[PDF]
2011
1. Ning Ning, Yi Kaijun, Huang Kejie, Shi Luping. 'Axonal Slow Integration Induced Persistent Firing Neuron Model and Spiking Network'. In Neural Information Processing. Springer Berlin Heidelberg, 2011.[PDF ]

　　

Book Chapter

2011
1. Kejie Huang, Yin Zhou, Xiaobo Wu, Wentai Liu and Zhi Yang. 'Design and Optimization ofInductive Power Link for Biomedical Applications'. Applied Biomedical Engineering, ISBN:978-953-307-256-2, 2011.[PDF]

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