數字邏輯與計算機設計——VHDL語言描述

《數字邏輯與計算機設計——VHDL語言描述》是2015年1月清華大學出版社出版的圖書，作者是Richard S· Sandige、Michael L· Sandige。

基本介紹

• 中文名：數字邏輯與計算機設計——VHDL語言描述
• 作者：Richard S. Sandige、Michael L. Sandige
• 出版時間：2015年1月
• 出版社：清華大學出版社
• ISBN：9787302386834
• 定價：99 元

內容簡介

本書由Richard S. Sandige和Michael L. Sandige所著。前者是加州理工州立大學的一名退休名譽教授，他在美國多所大學從事過教學工作，還在多家公司從事過研發工作，具有豐富的教學和技術開發經驗。後者則非常熱愛遊戲的研發，目前是WildTangent公司的首席工程師。兩位作者將本書分成數字設計和計算機設計兩部分內容，數字設計部分包括第1章至第9章的內容，計算機設計包括第10章至第25章的內容。此外，還撰寫了5個附錄，涵蓋了與前面25章的內容對應的34個實驗，以及實驗中涉及的軟體和硬體開發板的使用手冊等內容。

圖書目錄

Preface21

About the Authors28

Chapter 1Boolean Algebra, Boolean Functions, VHDL, and Gates1

1.1Introduction1

1.2Basics of Boolean Algebra1

1.2.1Venn Diagrams2

1.2.2Black Boxes for Boolean Functions3

1.2.3Basic Logic Symbols4

1.2.4Boolean Algebra Postulates7

1.2.5Boolean Algebra Theorems8

1.2.6Proving Boolean Algebra Theorems9

1.3Deriving Boolean Functions from Truth

Tables10

1.3.1Deriving Boolean Functions Using the 1s of the Functions10

1.3.2Deriving Boolean Functions Using the 0s of the Functions11

1.3.3Deriving Boolean Functions Using Minterms and Maxterms12

1.4Writing VHDL Designs for Simple Gate Functions15

1.4.1VHDL Design for a NOT Function15

1.4.2VHDL Design for an AND Function17

1.4.3VHDL Design for an OR Function18

1.4.4VHDL Design for an XOR Function19

1.4.5VHDL Design for a NAND Function21

1.4.6VHDL Design for a NOR Function22

1.4.7VHDL Design for an XNOR Function24

1.4.8VHDL Design for a BUFFER

Function26

1.4.9VHDL Design for any Boolean Function Written in Canonical Form27

1.5More about Logic Gates30

1.5.1Equivalent Gate Symbols30

1.5.2Functionally Complete Gates31

1.5.3Equivalent Gate Circuits32

1.5.4Compact Description Names for Gates32

1.5.5International Logic Symbols for Gates32

Problems34

數字邏輯與計算機設計——VHDL語言描述

Chapter 2Number Conversions, Codes, and Function Minimization37

2.1Introduction37

2.2Digital Circuits versus Analog Circuits37

2.2.1Digitized Signal for the Human Heart37

2.2.2Discrete Signals versus Continuous

Signals38

2.3Binary Number Conversions38

2.3.1Decimal, Binary, Octal, and Hexadecimal Numbers38

2.3.2 Conversion Techniques40

2.4Binary Codes45

2.4.1Minimum Number of Bits for Keypads and Keyboards45

2.4.2Commonly Used Codes: BCD, ASCII, and Others45

2.4.3Modulo2 Addition and Conversions between Binary and Reflective Gray

Code48

2.4.47Segment Code51

2.4.5VHDL Design for a Letter Display

System52

2.5Karnaugh Map Reduction Method54

2.5.1 The Karnaugh Map Explorer55

2.5.2 Using a 2Variable KMap56

2.5.3 Using a 3Variable KMap58

2.5.4 Using a 4Variable KMap60

2.5.5 Don’tCare Outputs61

Problems63

Chapter 3Introduction to Logic Circuit Analysis and Design67

3.1Introduction67

3.2Integrated Circuit Devices67

3.3Analyzing and Designing Logic Circuits69

3.3.1Analyzing and Designing Relay Logic Circuits69

3.3.2Analyzing IC Logic Circuits70

3.3.3Designing IC Logic Circuits71

3.4Generating Detailed Schematics74

3.5Designing Circuits in NAND/NAND and NOR/NOR Form76

3.6Propagation Delay Time78

3.7Decoders79

3.7.1Designing Logic Circuits with Decoders and Single Gates82

3.8Multiplexers85

3.8.1Designing Logic Circuits with MUXs87

3.9Hazards88

3.9.1Function Hazards88

3.9.2Logic Hazards89

Problems91

Chapter 4Combinational Logic Circuit Design with VHDL94

4.1Introduction94

4.2VHDL94

4.3The Library Part95

4.4The Entity Declaration96

4.5The Architecture Declaration97

4.5.1Comments about a Dataflow Design

Style98

4.5.2Comments about a Behavioral Design

Style98

4.5.3Comments about a Structural Design

Style98

4.6Dataflow Design Style99

4.7Behavioral Design Style102

4.8Structural Design Style106

4.9Implementing with Wires and Buses112

4.10VHDL Examples116

4.10.1Design with Scalar Inputs and

Outputs117

4.10.2Design with Vector Inputs and

Outputs118

4.10.3Common VHDL Constructs120

Problems121

Chapter 5Bistable Memory Device Design with VHDL125

5.1Introduction125

5.2Analyzing an SR NOR Latch125

5.2.1Simple On/Off Light Switch125

5.2.2Circuit Delay Model for an SR NOR Latch127

5.2.3Characteristic Table for an SR NOR Latch128

5.2.4Characteristic Equation for an SR NOR Latch129

5.2.5PS/NS Table for an SR NOR Latch129

5.2.6Timing Diagram for an SR NOR

Latch130

5.3Analyzing an SR NAND Latch132

5.3.1Circuit Delay Model for an SR NAND Latch132

5.3.2Characteristic Table for an SR NAND Latch132

5.3.3Characteristic Equation for an SR NAND Latch133

5.3.4PS/NS Table for an SR NAND

Latch133

5.3.5Timing Diagram for an SR NAND

Latch133

5.4Designing a Simple Clock134

5.5Designing a D Latch137

5.5.1Gated SR Latch Circuit Design137

5.5.2D Latch Circuit Design with SR

Latches138

5.5.3D Latch Circuit Design via the Characteristic Table for a D Latch139

5.5.4Timing Diagram for a D Latch140

5.5.5Creating a Clock via a D Latch141

5.5.6Creating an8bit D Latch142

5.6Designing D FlipFlop Circuits143

5.6.1Designing Master–Slave D FlipFlop Circuits143

5.6.2Designing D FlipFlop Circuits with SR NAND Latches146

5.6.3Timing Diagram for Positive EdgeTriggered D FlipFlop149

Problems150

Chapter 6Simple Finite State Machine Design with VHDL156

6.1Introduction156

6.2Synchronous Circuits156

6.3Creating Dtype FlipFlops in VHDL157

6.4Designing Simple Synchronous Circuits158

6.5Counter Design Using the Algorithmic Equation Method159

6.6Nonconventional Counter Design Using the Algorithmic Equation Method167

6.7Counter Design Using the Arithmetic

Method170

6.8Frequency Division (Slowing Down a Fast Clock Frequency)171

6.9Counter Design Using the PS/NS Tabular Method174

6.10Nonconventional Counter Design Using the PS/NS Tabular Method177

Problems178

Chapter 7Computer Circuits184

7.1Introduction184

7.2ThreeState Outputs and the Disconnected

State184

7.3Data Bus Sharing for a Microcomputer

System187

7.4More about XOR and XNOR Symbols and Functions190

7.4.1Odd and Even Functions191

7.4.2SingleBit Error Detection System192

7.4.3Comparators and Greater Than

Circuits194

7.5Adder Design197

7.5.1Designing a Half Adder Module197

7.5.2Designing a Full Adder Module198

7.6Designing and Using RippleCarry Adders and Subtractors200

7.7Propagation Delay Time for RippleCarry Adders203

7.8Designing Carry LookAhead Adders203

7.9Propagation Delay Time for Carry LookAhead Adders206

Problems206

Chapter 8Circuit Implementation

Techniques210

8.1Introduction210

8.2Programmable Logic Devices210

8.2.1PROMs and LUTs212

8.2.2PLAs213

8.2.3PALs or GALs213

8.2.4Designing with PROMs or LUTs214

8.2.5Designing with PLAs215

8.2.6Designing with PALs or GALs216

8.3Positive Logic Convention and Direct Polarity Indication217

8.3.1Signal Names217

8.3.2Analyzing Equivalent Circuits for the PLC and the DPI Systems218

8.4More about MUXs and DMUXs221

8.4.1Designing MUX Trees223

8.4.2Designing DMUX Trees223

Problems224

Chapter 9Complex Finite State Machine Design with VHDL227

9.1Introduction227

9.2Designing with the TwoProcess PS/NS

Method228

9.3Explanation of CPLDs and FPGAs and State Machine Encoding Styles231

9.4Summary of Finite State Machine Models234

9.5Designing Compact Encoded State Machines with Moore Outputs235

9.6Designing OneHot Encoded State Machines with Moore Outputs237

9.7Designing Compact Encoded State Machines with Moore and Mealy Outputs241

9.8Designing OneHot Encoded State Machines with Moore and Mealy Outputs243

9.9Using the Algorithmic Equation Method to Design Complex State Machines245

9.10Improving the Reliability of Complex State Machine Designs251

9.11Additional State Machine Design

Methods255

9.11.1TwoAssignment PS/NS Method256

9.11.2Hybrid PS/NS Method259

Problems262

Chapter 10Basic Computer Architectures279

10.1Introduction279

10.2Generic DataProcessing System or

Computer279

10.3HarvardType Computer and RISC Architecture280

10.4Princeton (von Neumann)Type Computer and CISC Architecture282

10.5Overview of VBC1 (Very Basic Computer 1)283

10.6Design Philosophy of VBC1283

10.7Programmer’s Register Model for VBC1286

10.8Instruction Set Architecture for VBC1287

10.9Format for Writing Assembly Language

Programs289

Problems290

Chapter 11Assembly Language Programming for VBC1292

11.1Introduction292

11.2Instruction Set for VBC1292

11.3The IN Instruction293

11.4The OUT Instruction296

11.5The MOV Instruction298

11.6The LOADI Instruction300

11.7The ADDI Instruction301

11.8The ADD Instruction303

11.9The SR0 Instruction304

11.10The JNZ Instruction306

11.11Programming Examples and Techniques for VBC1308

11.11.1Unconditional Jump308

11.11.2Labels308

11.11.3Loop Counter309

11.11.4Program Runs Amuck310

11.11.5Subtraction Instruction310

11.11.6Multiply Instruction312

11.11.7Divide Instruction312

Problems312

Chapter 12Designing Input/Output

Circuits316

12.1Introduction316

12.2Designing Steering Circuits316

12.3Designing Bus Steering Circuits318

12.4Designing Loadable Register Circuits319

12.5Designing Input Circuits321

12.5.1Designing an Input Circuit Driven by Four Slide Switches323

12.6Designing Output Circuits324

12.6.1Designing an Output Circuit to Drive Four LEDs325

12.6.2Designing an Output Circuit to Drive a 7Segment Display326

12.6.3A Closer Look at the Circuitry for Display 0328

12.7Combining Input and Output Circuits to Form a Simple I/O System329

12.8Alternate VHDL Design Styles332

Problems333

Chapter 13Designing Instruction Memory, Loading Program Counter, and Debounced Circuit335

13.1Introduction335

13.2Designing an Instruction Memory335

13.2.1Coding Alterations for Instruction Memory337

13.2.2Initializing Instruction Memory for VBC1 at Startup339

13.3Designing a Loading Program Counter342

13.4Designing a Debounced OnePulse

Circuit345

13.5Design Verification for a Debounced OnePulse Circuit348

Problems355

Chapter 14Designing Multiplexed Display Systems357

14.1Introduction357

14.2Multiplexed Display System for Four 7Segment LED Displays357

14.3Designing a Multiplexed Display System Using VHDL360

14.3.1Designing Module 1: A 4to1 MUX Array360

14.3.2Designing Module 2: A HEX Display Decoder361

14.3.3Designing Module 3: A 2bit Counter and a Frequency Divider362

14.3.4Designing Module 4: A 2to4

Decoder364

14.4Complete Design of a Multiplexed Display System Using a Flat Design Approach364

14.5Complete Design of a Multiplexed Display System Using a Hierarchal Design

Approach367

14.6Designing a Word Display System Using a Flat Design Approach372

Problems377

Chapter 15Designing Instruction Decoders379

15.1Introduction379

15.2Purpose of the Instruction Decoder379

15.3Instruction Decoder Truth Tables for the IN, OUT, and MOV Instructions380

15.4Designing an Instruction Decoder for the IN Instruction382

15.5Designing an Instruction Decoder for the OUT and MOV Instructions383

15.6Instruction Decoder Truth Table for the LOADI Instruction384

15.7Instruction Decoder Truth Table for the ADDI Instruction385

15.8Instruction Decoder Truth Table for the ADD Instruction386

15.9Instruction Decoder Truth Table for the SR0 Instruction387

15.10Designing an Instruction Decoder for the SR0 Instruction388

15.11Instruction Decoder Truth Table for the JNZ Instruction389

15.12Designing an Instruction Decoder for the JNZ Instruction391

15.13Designing an Instruction Decoder for

VBC1393

Problems393

Chapter 16Designing Arithmetic Logic

Units398

16.1Introduction398

16.2Utilization of the Arithmetic Logic Unit398

16.3Designing the LOADI Instruction Part of the ALU399

16.4Designing the ADDI Instruction Part of the ALU400

16.5Designing the ADD Instruction Part of the ALU401

16.6Designing the SR0 Instruction Part of the ALU401

16.7Designing an ALU for VBC1402

16.8Additional Circuit Designs with VHDL403

16.8.1Designing Additional ALU

Circuits403

16.8.2Designing Shifter Circuits406

16.8.3Designing Barrel Shifter Circuits409

16.8.4Designing Shift Register Circuits412

Problems414

Chapter 17Completing the Design for

VBC1416

17.1Introduction416

17.2Designing a Running Program Counter416

17.3Combining a Loading and a Running Program Counter419

17.4Designing a Run Frequency Circuit and a Speed Circuit421

17.5Designing Circuits to Provide a Loader for Instruction Memory for VBC1423

Problems424

Chapter 18Assembly Language Programming for VBC1E425

18.1Introduction425

18.2Instruction Summary425

18.3Input, Output, and Interrupt

Instructions427

18.4Data Memory Instructions432

18.5Arithmetic and Logic Instructions434

18.6Shift and Rotate Instructions437

18.7Jump, Jump Relative, and Halt

Instructions439

18.8More about Interrupts and Assembler Directives443

18.9Complete Instruction Set Summary for

VBC1E448

Problems449

Chapter 19Designing Input/Output Circuits for VBC1E458

19.1Introduction458

19.2Designing the Input Circuit for VBC1E458

19.3Instruction Decoder Truth Table for the Modifi ed IN Instruction for VBC1E460

19.4Designing the Output Circuit for

VBC1E462

19.5Instruction Decoder Truth Table for the Modifi ed OUT Instruction for VBC1E464

19.6Designing an Instruction Decoder for the Modifi ed IN and OUT Instructions for

VBC1E466

19.7Designing an Instruction Decoder for the LOADI, ADDI, and JNZ Instructions for VBC1E467

Problems468

Chapter 20Designing the Data Memory Circuit for VBC1E471

20.1Introduction471

20.2Designing the Data Memory for VBC1E471

20.3Designing Circuits to Select the Registers and Data for VBC1E475

20.4Instruction Decoder Truth Tables for the STORE and FETCH Instructions for

VBC1E475

20.5Designing an Instruction Decoder for the STORE and FETCH Instructions for

VBC1E478

20.6Designing an Instruction Decoder for the MOV Instruction for VBC1E479

Problems480

Chapter 21Designing the Arithmetic, Logic, Shift, Rotate, and Unconditional Jump Circuits for VBC1E482

21.1Introduction482

21.2Designing the Arithmetic and Logic Instructions Part of the ALU for

VBC1E482

21.3Designing the Instruction Decoder for the Arithmetic and Logic Instructions for

VBC1E484

21.4Designing the Shift and Rotate Instructions Part of the ALU for VBC1E485

21.5Designing the Instruction Decoder for the Shift and Rotate Instructions for VBC1E486

21.6Designing the JMP and JMPR Circuits for VBC1E488

21.7Designing the Instruction Decoder for the JMP and JMPR Instructions for VBC1E489

Problems490

Chapter 22Designing a Circuit to Prevent Program Execution During Manual Loading for VBC1E493

22.1Introduction493

22.2Designing a Circuit to Modify Manual Loading for VBC1E493

22.3Modifying the Instruction Decoder for Manual Loading for VBC1E495

Problems495

Chapter 23Designing Extended Instruction Memory for VBC1E496

23.1Introduction496

23.2Modifying the Instruction Memory to Add Extended Instruction Memory for

VBC1E496

23.3Modifying the Running Program Counter Circuit for VBC1E500

23.4Modifying the Proper Address Circuit for VBC1E501

23.5Modifying the Loading Program Counter Circuit for VBC1E501

23.6Modifying the JMPR Circuit for VBC1E502

Problems502

Chapter 24Designing the Software Interrupt Circuits for VBC1E504

24.1Introduction504

24.2Designing the Modified Circuit for the Running Program Counter and the Select Circuit for VBC1E504

24.3Designing the Circuit to Store PCPLUS1 for VBC1E509

24.4Instruction Decoder Truth Tables for the INT and IRET Instructions for VBC1E510

24.5Designing the Instruction Decoder for the INT and IRET Instructions for VBC1E511

Problems513

Chapter 25Completing the Design for

VBC1E516

25.1Introduction516

25.2Designing a Debounced OnePulse Trigger Interrupt Circuit and Modifying the RPC Circuit for VBC1E516

25.3Designing Circuits for Displaying the Signal RETAfor VBC1E521

25.4Designing Circuits to Provide a Loader for Instruction Memory for VBC1E525

Problems525

Appendices

ALaboratory Experiments528

Experiment 1A: Designing and Simulating Gates528

Experiment 1B: Completing the Design Cycle534

Experiment 2: Designing and Testing a Keypad Encoder System539

Experiment 3: Designing and Testing a Check Gates System542

Experiment 4: Designing and Testing a Custom Decimal Display Decoder System546

Experiment 5A: Designing and Testing a D Latch and a D FlipFlop with a CLR Input549

Experiment 5B: Designing and Testing an 8bit Register and a D FlipFlop with a PRE

Input553

Experiment 6A: Designing and Testing a Simple Counter System—A OneHot Up Counter with 8 Bits558

Experiment 6B: Designing and Testing a Simple Counter System—A Gray Code Counter with 2 Bits562

Experiment 6C: Designing and Testing a Simple Nonconventional Counter System—A Robot Eye Circuit565

Experiment 6D: Designing and Testing a Simple Nonconventional Counter—A Smiley Face Circuit569

Experiment 7A: Designing and Testing a Simple Error Detection System Using a Flat Design Approach572

Experiment 7B: Designing and Testing a 4bit Simple AdderSubtractor System Using a Hierarchal Design Approach577

Experiment 8: Designing and Testing a LUT Design System Using a Flat Design

Approach580

Experiment 9A: Designing and Testing a OneHot Up/ Down Counter System Using a Flat Design Approach584

Experiment 9B: Designing and Testing a 10State Counter System Using a Hierarchal Design Approach589

Experiment 10: Working with EASY1 (Editor/Assembler/ Simulator) for VBC1593

Experiment 11: Writing and Simulating Programs for VBC1 with EASY1598

Experiment 12: Designing and Testing VBC1 (Data Path Unit)600

Experiment 13: Designing and Testing VBC1 (Instruction Memory Unit)605

Experiment 14: Designing and Testing VBC1 (Monitor System)609

Experiment 15: Designing and Testing VBC1 (Instruction Decoder )613

Experiment 16: Designing and Testing VBC1 (Arithmetic Logic Unit)617

Experiment 17: Designing and Testing VBC1 (Final Hardware Design for VBC1)621

Experiment 17L: Designing a Loader for Instruction Memory for VBC1626

Experiment 18: Writing Assembly Language Programs and Running Them on VBC1632

Experiment 19: Designing and Testing VBC1E (IN, OUT, and Unchanged Instructions)635

Experiment 20: Designing and Testing VBC1E (MOV and Data Memory Instructions)640

Experiment 21: Designing and Testing VBC1E (Almost All Instructions)645

Experiment 22: Designing and Testing VBC1E (Modifi ed Manual Loading)651

Experiment 23: Designing and Testing VBC1E (Add Extended Instruction Memory)654

Experiment 24: Designing and Testing VBC1E (INT and IRET Instructions)658

Experiment 25: Designing and Testing VBC1E (Final Hardware Design for VBC1E)663

Experiment 25L: Designing a Loader for Instruction Memory for VBC1E668

BObtaining Simulations via the VHDL TestBench Program675

B.1Introduction675

B.2Example 1—Combinational Logic Design (project: AND_3)675

B.3Example 2—Synchronous Sequential Logic Design (project: DFF)679

CFPGA Pin Connections—Handy Reference683

C.1BASYS 2 Board683

C.2NEXYS 2 Board684

C.3Memory Loader I/O Pin Connections for the FPGAs on the BASYS 2 and NEXYS 2

Board685

C.4FX2 MIB (Module Interface Board)—Addon Board for NEXYS 2686

DEASY1 Tutorial687

D.1Introduction687

D.2EASY1 Screen or GUI687

D.3EASY1 Layout687

D.4How to Use EASY1689

D.5Example 1—A Simple Input/Output

Program689

D.6Example 2—Input/Output Program Modified to Run Continuously695

D.7Example 3—A Simple State Machine

Program696

D.8Example 4—A Complex State Machine

Program696

D.9Example 5—Generating Time Delays698

D.10Using EASY1 to Generate Machine Code for VBC1699

EThree Methods for Loading Instructionsinto Memory701

E.1Loading Memory Manually701

E.2Initializing Memory at Startup702

E.3Loading Memory via the Memory Loader Program703

Index705

第1章布爾代數、布爾函式、VHDL和門1

1.1引言1

1.2布爾代數基礎1

1.2.1維恩圖2

1.2.2布爾函式的黑盒子3

1.2.3基本邏輯符號4

1.2.4布爾代數公理7

1.2.5布爾代數定理8

1.2.6布爾代數定理的證明9

1.3從真值表推出布爾函式10

1.3.1用函式的1值推出布爾函式10

1.3.2用函式的0值推出布爾函式11

1.3.3用最小項和最大項推出布爾函式12

1.4簡單門函式的VHDL設計15

1.4.1NOT函式的VHDL設計15

1.4.2AND函式的VHDL設計17

1.4.3OR函式的VHDL設計18

1.4.4XOR函式的VHDL設計19

1.4.5NAND函式的VHDL設計21

1.4.6NOR函式的VHDL設計22

1.4.7XNOR函式的VHDL設計24

1.4.8BUFFER函式的VHDL設計26

1.4.9用標準形式給出的任意布爾函式的VHDL設計27

1.5有關邏輯門的更多內容30

1.5.1等價門符號30

1.5.2全功能門31

1.5.3等價門電路32

1.5.4門的簡化描述名稱32

1.5.5門的國際邏輯符號32

習題34

第2章數制轉換、碼制和函式最簡化37

2.1引言37

2.2數字電路與模擬電路37

2.2.1人類心臟的數位化信號37

2.2.2離散信號與連續信號38

2.3二進制數制轉換38

2.3.1十進制數、二進制數、八進制數和十六進制數38

2.3.2轉換技術40

2.4二進制碼制45

2.4.1小鍵盤和鍵盤的最少比特表示45

2.4.2常見碼制： BCD，ASCII，以及其他45

2.4.3二進制和反射格雷碼之間的模2加法和轉換48

2.4.4七段碼51

2.4.5字母顯示系統的VHDL設計52

2.5卡諾圖化簡方法54

2.5.1卡諾圖資源管理器55

2.5.2使用兩變數卡諾圖56

2.5.3使用三變數卡諾圖58

2.5.4使用四變數卡諾圖60

2.5.5無關的輸出61

習題63

第3章邏輯電路分析和設計簡介67

3.1引言67

3.2積體電路器件67

3.3分析和設計邏輯電路69

3.3.1分析和設計繼電器邏輯電路69

3.3.2分析IC邏輯電路70

3.3.3設計IC邏輯電路71

3.4生成詳細的原理圖74

3.5用與非/與非和或非/或非形式設計電路76

3.6傳輸延時78

3.7解碼器79

3.7.1用解碼器和單個門設計邏輯電路82

3.8多路選擇器85

3.8.1用多路選擇器設計邏輯電路87

3.9險象88

3.9.1功能險象88

3.9.2邏輯險象89

習題91

第4章組合邏輯電路的VHDL設計94

4.1引言94

4.2VHDL94

4.3庫組成95

4.4實體聲明96

4.5結構體聲明97

4.5.1數據流設計風格評價98

4.5.2行為設計風格評價98

4.5.3結構設計風格評價98

4.6數據流設計風格99

4.7行為設計風格102

4.8結構設計風格106

4.9用連線和匯流排實現112

4.10VHDL設計實例116

4.10.1用標量輸入和輸出設計117

4.10.2用向量輸入和輸出設計118

4.10.3通用VHDL體系結構120

習題121

第5章雙穩態存儲器件的VHDL設計125

5.1引言125

5.2SR NOR鎖存器分析125

5.2.1簡單的電燈開關125

5.2.2SR NOR鎖存器的電路延遲模型127

5.2.3SR NOR鎖存器的特性表128

5.2.4SR NOR鎖存器的特徵方程129

5.2.5SR NOR 鎖存器的PS/NS表129

5.2.6SR NOR鎖存器的時序圖130

5.3SR NAND鎖存器分析132

5.3.1SR NAND鎖存器電路延遲模型132

5.3.2SR NAND鎖存器的特性表132

5.3.3SR NAND鎖存器的特徵方程133

5.3.4SR NAND鎖存器的PS/NS表133

5.3.5SR 與非鎖存器的時序圖133

5.4設計一個簡單的時鐘134

5.5設計一個D鎖存器137

5.5.1門控SR鎖存器電路設計137

5.5.2用SR鎖存器設計D鎖存器電路138

5.5.3利用D鎖存器的特性表來設計D鎖存器電路139

5.5.4D鎖存器的時序圖140

5.5.5用D鎖存器構造一個時鐘141

5.5.6構造一個8比特的D鎖存器142

5.6設計D觸發器電路143

5.6.1設計主從型D觸發器電路143

5.6.2用SR與非鎖存器設計D觸發器146

5.6.3上升沿觸發的D觸發器的時序圖149

習題150

第6章簡單有限狀態機的VHDL設計156

6.1引言156

6.2同步電路156

6.3用VHDL構造一個D型觸發器157

6.4設計簡單的同步電路158

6.5用算法公式法設計計數器159

6.6用算法公式法設計非傳統計數器167

6.7用算術法設計計數器170

6.8分頻（降低一個快時鐘的頻率）171

6.9用PS/NS表格法設計計數器174

6.10用PS/NS表格法設計非傳統計數器177

習題178

第7章計算機電路184

7.1引言184

7.2三態輸出與斷開狀態184

7.3微計算機系統的數據匯流排共享187

7.4深入了解XOR和XNOR符號及功能190

7.4.1奇函式和偶函式191

7.4.2單比特錯誤檢測系統192

7.4.3比較器和大於電路194

7.5加法器設計197

7.5.1半加器模組的設計197

7.5.2全加器模組的設計198

7.6設計及使用行波進位加法器和減法器200

7.7行波進位加法器的傳播延遲時間203

7.8設計超前進位加法器203

7.9超前進位加法器的傳播延遲時間206

習題206

第8章電路實現技術210

8.1引言210

8.2可程式邏輯器件210

8.2.1可程式唯讀存儲器（PROM）和查找表（LUT）212

8.2.2可程式邏輯陣列（PLA）213

8.2.3可程式陣列邏輯（PAL）或者通用陣列邏輯（GAL）213

8.2.4使用PROM或者LUT進行

電路設計214

8.2.5使用PLA進行電路設計215

8.2.6使用PAL或者GAL進行電路設計216

8.3正邏輯規則和直接極性標誌217

8.3.1信號名稱217

8.3.2PLC和DPI系統的等效電路分析218

8.4更多關於多路選擇器（MUX）和數據分路器（DMUX）的內容221

8.4.1MUX樹設計223

8.4.2DMUX樹設計223

習題224

第9章複雜有限狀態機的VHDL設計227

9.1引言227

9.2基於雙進程PS/NS方法的設計228

9.3CPLD、FPGA和狀態機編碼風格淺析231

9.4有限狀態機模型總結 234

9.5利用摩爾輸出設計緊湊編碼狀態機 235

9.6利用摩爾輸出設計單熱點編碼狀態機 237

9.7利用摩爾和米利輸出設計緊湊編碼

狀態機 241

9.8利用摩爾和米利輸出設計單熱點編碼

狀態機 243

9.9利用算法公式法設計複雜狀態機 245

9.10提高複雜狀態機的可靠性 251

9.11其他狀態機設計方法 255

9.11.1雙分配PS/NS方法256

9.11.2混合PS/NS方法259

習題262

第10章基本的計算機體系結構279

10.1引言279

10.2通用數據處理系統或計算機279

10.3哈佛型計算機和RISC體系結構280

10.4普林斯頓（馮·諾依曼）型計算機和CISC體系結構282

10.5VBC1概述283

10.6VBC1設計原理283

10.7VBC1編程器暫存器模型286

10.8VBC1指令集體系結構287

10.9彙編語言程式的編寫格式289

習題290

第11章VBC1的彙編語言編程292

11.1引言292

11.2VBC1指令集292

11.3IN指令293

11.4OUT指令296

11.5MOV指令298

11.6LOADI指令300

11.7ADDI指令301

11.8ADD指令303

11.9SR0指令304

11.10JNZ指令306

11.11VBC1編程實例和技術308

11.11.1無條件跳轉308

11.11.2標籤308

11.11.3循環計數器309

11.11.4程式“橫行”310

11.11.5減法指令310

11.11.6乘法指令312

11.11.7除法指令312

習題312

第12章設計輸入/輸出電路316

12.1引言316

12.2設計仲裁電路316

12.3設計匯流排仲裁電路318

12.4設計可載入暫存器電路319

12.5設計輸入電路321

12.5.1設計由4個滑動開關驅動的輸入

電路323

12.6設計輸出電路324

12.6.1設計驅動4個LED的輸出電路325

12.6.2設計一個可以驅動7段顯示器的輸出電路326

12.6.3仔細觀察顯示0的電路328

12.7結合輸入輸出電路搭建一個簡單I/O

系統329

12.8可選的VHDL設計風格332

習題333

第13章設計指令存儲器、載入程式計數器和去抖動電路335

13.1引言335

13.2設計一個指令存儲器335

13.2.1指令存儲器的代碼變形337

13.2.2在啟動階段初始化VBC1的指令

存儲器339

13.3設計一個載入程式計數器342

13.4設計一個去抖動單脈衝電路345

13.5設計去抖動單脈衝電路的驗證電路348

習題355

第14章設計多路顯示系統357

14.1引言357

14.2四個7段LED顯示器構成的多路顯示

系統357

14.3用VHDL設計多路顯示系統360

14.3.1設計模組一： 四選一MUX陣列360

14.3.2設計模組二： 十六進制顯示

解碼器361

14.3.3設計模組三： 2比特計數器和

分頻器362

14.3.4設計模組四： 24線解碼器364

14.4用平面設計方法設計多路顯示系統364

14.5用層次化設計方法設計多路顯示系統367

14.6利用平面設計方法設計一個字元顯示

系統372

習題377

第15章設計指令解碼器379

15.1引言379

15.2指令解碼器設計目標379

15.3指令IN、OUT和MOV的指令解碼器

真值表380

15.4設計指令IN的指令解碼器382

15.5設計指令OUT和MOV的指令解碼器383

15.6指令LOADI的指令解碼器真值表384

15.7指令ADDI的指令解碼器真值表385

15.8指令ADD的指令解碼器真值表386

15.9指令SR0的指令解碼器真值表387

15.10設計指令SR0的指令解碼器388

15.11指令JNZ的指令解碼器真值表389

15.12設計指令JNZ的指令解碼器391

15.13設計VBC1的指令解碼器393

習題393

第16章設計算術邏輯單元398

16.1引言398

16.2算術邏輯單元的使用398

16.3設計ALU的LOADI指令部分399

16.4設計ALU的ADDI指令部分400

16.5設計ALU的ADD指令部分401

16.6設計ALU的SR0指令部分401

16.7為VBC1設計一個ALU402

16.8用VHDL設計的附加電路403

16.8.1設計額外的ALU電路403

16.8.2設計移位電路406

16.8.3設計桶形移位電路409

16.8.4設計移位暫存器電路412

習題414

第17章完成VBC1的設計416

17.1引言416

17.2設計一個運行程式計數器416

17.3將載入程式計數器與運行程式計數器結合起來419

17.4設計運行頻率電路和速度電路421

17.5設計VBC1的指令存儲器的載入電路423

習題424

第18章VBC1E的彙編語言編程425

18.1引言425

18.2指令總結425

18.3輸入、輸出與中斷指令427

18.4數據存儲指令432

18.5算術指令與邏輯指令434

18.6移位指令與循環移位指令437

18.7跳轉指令、相對跳轉指令與暫停指令439

18.8關於中斷與彙編器命令的更多內容443

18.9VBC1E完整指令集總結448

習題449

第19章設計VBC1E的輸入/輸出電路458

19.1引言458

19.2VBC1E的輸入電路設計458

19.3VBC1E的修改後IN指令的指令解碼

真值表460

19.4VBC1E的輸出電路設計462

19.5VBC1E的修改後OUT指令的指令解碼

真值表464

19.6VBC1E的修改後IN和OUT指令的指令解碼器設計4664

19.7VBC1E的LOADI、ADDI和JNZ指令的指令解碼器設計467

習題468

第20章設計VBC1E的數據存儲器電路471

20.1引言471

20.2設計VBC1E的數據存儲器471

20.3設計VBC1E的暫存器和數據選擇

電路475

20.4VBC1E的STORE和FETCH指令的指令解碼器真值表475

20.5設計VBC1E的STORE和FETCH指令的指令解碼器478

20.6設計VBC1E的MOV指令的指令

解碼器479

習題480

第21章設計VBC1E的算術、邏輯、移位、旋轉和無條件跳轉電路482

21.1引言482

21.2VBC1E ALU的算術和邏輯指令部分

設計 482

21.3VBC1E的算術和邏輯指令解碼器

設計 484

21.4VBC1E ALU的移位和旋轉指令部分

設計 485

21.5VBC1E的移位和旋轉指令解碼器

設計 486

21.6VBC1E的JMP和JMPR電路設計 488

21.7VBC1E的JMP和JMPR指令解碼器

設計489

習題490

第22章設計VBC1E中手動載入時阻止程式執行的電路493

22.1引言493

22.2設計VBC1E中修改手動載入的電路493

22.3修改手動載入時VBC1E中的指令

解碼器495

習題495

第23章設計VBC1E的擴展指令存儲器496

23.1引言496

23.2為VBC1E修改指令存儲器以增加擴展指令存儲器496

23.3為VBC1E修改運行程式計數器電路500

23.4為VBC1E修改合理地址電路501

23.5為VBC1E修改載入程式計數器電路501

23.6為VBC1E修改JMPR電路502

習題502

第24章設計VBC1E的軟體中斷電路504

24.1引言504

24.2設計VBC1E的運行程式計數器與選擇電路的改進電路504

24.3設計VBC1E的存儲PCPLUS1的電路509

24.4VBC1E的INT和IRET指令的指令解碼器真值表510

24.5設計VBC1E的INT和IRET指令的指令解碼器511

習題513

第25章完成VBC1E的設計516

25.1引言516

25.2設計VBC1E的去抖動單脈衝觸發

中斷電路並修改RPC電路516

25.3設計VBC1E的RETA信號的顯示

電路521

25.4設計VBC1E的提供指令存儲器的

載入器功能的電路525

習題525

附錄

附錄A實驗案例528

實驗1A： 門電路的設計與仿真528

實驗1B： 完成設計流程534

實驗2： 鍵盤編碼系統的設計與測試539

實驗3： 門電路檢驗系統的設計與測試542

實驗4： 自定義十進制顯示解碼系統的設計與

測試546

實驗5A： D鎖存器與帶CLR輸入的D觸發器的

設計與測試549

實驗5B： 8位暫存器與帶PRE輸入的D觸發器

的設計與測試553

實驗6A： 簡單計數系統的設計與測試——8位單熱遞增計數器558

實驗6B： 簡單計數器系統的設計與測試——兩位格雷碼計數器562

實驗6C： 簡單非常規計數系統的設計與測試——機器眼電路565

實驗6D： 簡單非常規計數系統的設計與測試——笑臉電路569

實驗7A： 用平面設計方法進行簡單錯誤檢測系統的設計與測試572

實驗7B： 用層次化設計方法進行簡單4位加減系統的設計與測試577

實驗8： 利用平面設計方法進行LUT系統的設計與測試580

實驗9A： 用平面設計方法進行單熱遞增/遞減計數系統的設計與測試584

實驗9B： 用層次化設計方法進行十狀態計數系統的設計與測試589

實驗10： VBC1系統EASY1（編輯器/彙編器/仿真器）的使用593

實驗11： 用EASY1編寫和仿真VBC1程式598

實驗12： VBC1的設計與測試（數據通路單元）600

實驗13： VBC1的設計與測試（指令存儲單元）605

實驗14： VBC1的設計與測試（顯示系統）609

實驗15： VBC1的設計與測試（指令解碼器）613

實驗16： VBC1的設計與測試（算術邏輯單元）617

實驗17： VBC1的設計與測試（最終硬體設計）621

實驗17L： 設計VBC1的指令存儲器載入器626

實驗18： 在VBC1上編寫並運行彙編程式632

實驗19： VBC1E的設計與測試（IN、OUT和未修改的指令）635

實驗20： VBC1E的設計與測試（MOV和數據存儲器指令）640

實驗21： VBC1E的設計與測試（大部分指令）645

實驗22： VBC1E的設計與測試（修改後的手動載入）651

實驗23： VBC1E的設計與測試（添加擴展指令存儲器）654

實驗24： VBC1E的設計與測試（INT和IRET指令）658

實驗25： VBC1E的設計與測試（最終硬體設計）663

實驗25L： 設計VBC1E的指令存儲器載入器668

附錄B用VHDL測試平台程式進行仿真675

B.1簡介675

B.2例1： 組合邏輯設計（工程AND_3）675

B.3例2： 同步時序邏輯設計（工程DFF）679

附錄CFPGA管腳連線關係查詢手冊683

C.1BASYS 2開發板683

C.2NEXYS 2開發板684

C.3BASYS 2及NEXYS 2開發板上FPGA存儲載入器的I/O引腳接口685

C.4FX2MIB（模組轉接板）： NEXYS 2外加

電路板686

附錄DEASY1 教程687

D.1簡介687

D.2EASY1用戶界面687

D.3EASY1界面布局687

D.4如何使用EASY1689

D.5例1： 簡單輸入輸出程式689

D.6例2： 修改後能夠一直執行的輸入/輸出

程式695

D.7例3： 簡單狀態機程式696

D.8例4： 複雜狀態機程式696

D.9例5： 產生延時698

D.10用EASY1產生VBC1平台的機器碼699

附錄E將指令載入到存儲器中的三種方法701

E.1手動載入存儲器701

E.2在啟動時初始化存儲器內容702

E.3通過存儲器載入程式載入存儲器703

索引705