劉勇攀，男，博士，清華大學電子工程系教授，電路與系統所所長。
基本介紹
- 中文名：劉勇攀
- 畢業院校：清華大學
- 學位/學歷：博士
- 職業：教師
- 專業方向：專用領域人工智慧晶片及架構，包括感算一體、目標檢測
- 職務：電路與系統所所長
- 任職院校：清華大學電子工程系
個人經歷,研究方向,學術成果,榮譽獎項,
個人經歷
教育經歷：
2004-2007年， 清華大學電子工程系，博士
1995-2002年， 清華大學電子工程系，本碩連讀
工作履歷：
2020- ， 清華大學電子工程系，長聘教授
2017-2019年， 清華大學電子工程系，長聘副教授，研究員
2017年4-6月，香港城市大學計算機科學系，訪問學者
2014年7-9月，美國賓夕法尼亞州立大學計算機科學系，訪問學者
2007-2016年， 清華大學電子工程系，助理研究員和副研究員
2004-2007年， 清華大學電子工程系，博士
2002-2004年， 清華大學電子工程系，助研
研究方向
1、 專用領域人工智慧晶片及架構，包括感算一體、目標檢測、視頻壓縮和自動駕駛
2、 基於新型器件的計算存儲晶片及架構，包括存算一體、非易失處理器和自供能電路
3、 智慧型物聯網電路與系統，包括功耗模型與評估、大面積感知系統和邊緣智慧型物聯網
學術成果
學術論文
[1] Jinshan Yue, Zhe Yuan, Xiaoyu Feng, Yifan He, Zhixiao Zhang, Xin Si, Ruhui Liu, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu*, A 65nm Computing-in-Memory Based CNN Processor with 2.9-35.8TOP/W System Energy Efficiency Using Dynamic Sparsity Performance Scaling Architecture and Energy Efficient Inter/Intra Macro Data Reuse, IEEE International Solid-state Circuits Conference (ISSCC), Accepted, 2020.
[2] Zhe Yuan, Yixiong Yang, Jinshan Yue, Ruoyang Liu,Xiaoyu Feng, Zhiting Lin, Xiulong Wu, Xueqing Li, Huazhong Yang, Yongpan Liu*, A 65nm 24.7 uJ/Frame 12.3 mW Activation Similarity Aware Convolutional Neural Network Video Processor Using Hybrid Precision Inter Frame Data Reuse and Mixed-Bit-Width Difference Frame Data Codec, IEEE International Solid-state Circuits Conference (ISSCC), Accepted, 2020.
[3] Yongpan Liu*, Fang Su, Yixiong Yang, Zhibo Wang, Yiqun Wang, Zewei Li, Xueqing Li, , Ryuji Yoshimura, Takashi Naiki, Takashi Tsuwa, Takahiko Saito, Zhongjun Wang, Koji Taniuchi, and Huazhong Yang, A 130-nm Ferroelectric Nonvolatile System-On-Chip with Direct Peripheral Restore Architecture for Transient Computing System，IEEE Journal of Solid-State Circuits (JSSC), 2019, 54(3): 885 - 895
[4] Jinshan Yue, Ruoyang Liu, Wenyu Sun, Zhe Yuan, Zhibo Wang, Yung-Ning Tu, Yi-Ju Chen, Ao Ren, Yanzhi Wang, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu*, A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural- Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1× Higher TOPS/mm2 and 6T HBST-TRAM-Based 2D Data-Reuse Architecture, IEEE International Solid-state Circuits Conference (ISSCC), pp. 138-140.
[5] Zhe Yuan, Yongpan Liu*, Jinshan Yue, Yixiong Yang, Jingyu Wang, Xiaoyu Feng, Xueqing Li Huazhong Yang, STICKER: An Energy Efficient Multi-Sparsity Compatible Accelerator for Deep Convolutional Neural Networks in 65nm CMOS, IEEE Journal of Solid-State Circuits (JSSC), Early Access, 2019: 1-13
[6] J Wu, H Zhong, K Ni, Yongpan Liu, H Yang, X Li, “A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs”, Proceedings of the 56th Annual Design Automation Conference (DAC), 2019.
[7] Zhe Yuan, Jinshan Yue, Huanrui Yang, Zhibo Wang, Jinyang Li, Yixiong Yang, Qingwei Guo, Xueqing Li, Meng-Fan Chang, Huazhong Yang, Yongpan Liu*, “STICKER: A 0.41-62.1 TOPS/W 8bit neural network processor with multi-sparsity compatible convolution arrays and online tuning acceleration for fully connected layers”, VLSI Circuits (VLSI), 2018 Symposium on. 2018: 33-34
[8] Patrick Cronin, Chengmo Yang, Yongpan Liu, “A collaborative defense against wear out attacks in non-volatile processors”, Design Automation Conference (DAC), 2018: 88:1-88:6.
[9] Zhibo Wang, Yongpan Liu*, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Jinyang Li, Chien-Chen Lin, Wei-Hao Chen, Hsiao-Yun Chiu, Wei-En Lin, Ya-Chin King, Chrong-Jung Lin, Pedram Khalili Amiri, Kang-Lung Wang, Meng-Fan Chang, and Huazhong Yang, A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving ＞4x Faster Clock Frequency and＞6x Higher Restore Speed”, IEEE Journal of Solid-State Circuits (JSSC), 2017, 52(10): 2769-2785.
[10] Fang Su, Wei-Hao Chen, Lixue Xia, Chieh-Pu Lo, Tianqi Tang, Zhibo Wang, Kuo-Hsiang Hsu, Ming Cheng, Jun-Yi Li, Yuan Xie, Yu Wang, Meng-Fan Chang, Huazhong Yang, Yongpan Liu*, A 462GOPs/J RRAM-Based Nonvolatile Intelligent Processor for Energy Harvesting IoE System Featuring Nonvolatile Logics and Processing-In-Memory”, VLSI Circuits (VLSI), 2017 Symposium on. IEEE, 2017: C260-C261.
[11] Zhibo Wang, Fang Su, Yiqun Wang, Zewei Li, Xueqing Li, Ryuji Yoshimura, Takashi Naiki, Takashi Tsuwa, Takahiko Saito, Zhongjun Wang, Koji Taniuchi, Meng-Fan Chang, Huazhong Yang, Yongpan Liu*, “A 130nm FeRAM-Based Parallel Recovery Nonvolatile SOC for Normally-OFF Operations with 3.9× Faster Running Speed and 11× Higher Energy Efficiency Using Fast Power-On Detection and Nonvolatile Radio Controller”, VLSI Circuits (VLSI), 2017 Symposium on. IEEE, 2017: C336-C337.
[12] Su Fang, Yongpan Liu*, Yiqun Wang, Huazhong Yang, “A Ferroelectric Nonvolatile Processor with 46 μs System-Level Wake-up Time and 14 μs Sleep Time for Energy Harvesting Applications”, IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2017, 64(3): 596-607.
[13] Yongpan Liu*; Zhibo Wang; Albert Lee; Fang Su; Chieh-Pu Lo; Zhe Yuan; Chien-Chen Lin; Qi Wei; Yu Wang; Ya-Chin King; Chrong-Jung Lin; Pedram Khalili; Kang-Lung Wang; Meng-Fan Chang; Huazhong Yang, “A 65nm ReRAM-Enabled Nonvolatile Processor with 6x Reduction in Restore Time and 4x Higher Clock Frequency Using Adaptive Data Retention and Self-Write-Termination Nonvolatile Logics”, IEEE International Solid-state Circuits Conference (ISSCC), 2016, pp. 84-86.
[14] Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang and Yuan Xie, “PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory” ,43rd ACM/IEEE International Symposium on Computer Architecture (ISCA), 2016, pp.1-13.
[15] Yongpan Liu*, Zewei Li, Hehe Li, Yiqun Wang, Xueqing Li, Kaisheng Ma, Shuangchen Li, Meng-Fan Chang, Sampson John,Yuan Xie, Jiwu Shu, and Huazhong Yang, “Ambient Energy Harvesting Nonvolatile Processors: From Circuit to System”, Proceedings of the Design Automation Conference (DAC), 2015, pp.1-6.
[16] 劉勇攀，袁哲，岳金山，楊華中等，一種套用於卷積神經網路的處理器。
[17] 龍衡宇，劉勇攀，楊華中，一種能量分配的方法和裝置。
[18] 龍衡宇，劉勇攀，應蓓華，楊華中，一種自適應劃分簇的方法及系統。
研究項目
1、 新原理存儲器件的存內計算關鍵技術研究，國家自然科學基金重點項目，2020-2025，項目負責人
2、 存算一體器件及其計算新架構，國家重點研發計畫，2019-2024，課題負責人
3、 智慧型晶片IP，重點項目，2019-2020，課題負責人
4、 智慧型數據存儲，重點項目，2019-2021，項目負責人
5、 CMOS無線體域網收發器晶片技術，重點項目，2017-2020，項目負責人
榮譽獎項
圍繞後摩爾時代新型器件與人工智慧套用帶來的挑戰與機遇，開展高能效電路與系統研究。（1）針對基於新型存儲器件的計算理論與架構缺失，提出了自供能電路理論和存算融合的非易失計算架構，發明了非易失處理器THU10XN系列晶片，突破了傳統CMOS計算晶片能效與計算模式的瓶頸；（2）針對新興深度學習套用對算力快速提升的挑戰，提出領域專用智慧型算芯一體的協同理論與系統架構，發明了多維度稀疏自適應智慧型計算架構和系列晶片，突破了傳統智慧型晶片能效與最佳化維度局限；（3）針對智慧型製造等重大需求，提出了基於智慧型邊緣計算晶片的物聯網感知、調度與端邊雲協同最佳化技術，轉移至湃方科技和源清慧虹等創業公司進行產業化。
擔任國家自然科學基金會評專家和創新特區項目論證專家，主持自然科學基金重點，國家重點研發計畫等重點項目10餘項。曾獲教育部技術發明一等獎，中國公路學會科學技術一等獎和電子學會科學技術二等獎。近年發表JSSC/TCAD/TCAS等 IEEE/ACM Trans論文35篇，ISSCC/DAC/VLSI在內會議論文85篇。2017年入選國際電子設計自動化領域DAC under 40歲以下發明創新獎，ASP-DAC 2017最佳論文，IEEE Micro Top Pick 2016，HPCA2015最佳論文以及低功耗電子系統設計競賽獎ISLPED2012,2013和2019，2019紐倫堡發明展銀獎等。擔任IEEE TCAD/TCAS-II，IET CPS編委，ASPDAC 2020設計自動化會議秘書長，NVMSA 2019非易失存儲會議技術委員會主席，IWCR2018跨層可靠性會議主席，AWSSS2016智慧型感測會議主席，A-SSCC2019智慧型晶片Panelist和DAC, DATE, ASPDAC, ISLPED，A-SSCC技術委員。
