賽靈思公司（Xilinx, Inc）2007推出業界套用最廣泛的集成軟體環境（ISE™）設計套件的最新版本ISE 9.1i。
基本介紹
- 中文名：賽靈思邏輯設計環境
- 外文名：Xilinx ISE 9.1i
- 釋放時間：2007.3月
- 性質：可程式邏輯設計解決方案
基本信息,其他信息,
基本信息
中文名: 賽靈思邏輯設計環境ISE 9.1i 英文名: Xilinx ISE 9.1i
Xilinx ISE 9.1i
Xilinx ISE 9.1 終於於2007.3月釋放。業界最完整的可程式邏輯設計解決方案，用於實現最優性能、功率管理、降低成本和提高生產率。 ISE 9.1i 利用新 SmartCompile 技術，來幫助用戶在更少的時間內實現業內最快速的 FPGA 性能！ISE™ 9.1i 是 Xilinx 最新推出的業內領先的設計工具，其性能比競爭解決方案平均快 30%。 新 SmartCompile 技術讓您能夠更快、更輕鬆地實現時序收斂。
賽靈思公司（Xilinx, Inc）2007推出業界套用最廣泛的集成軟體環境（ISE™）設計套件的最新版本ISE 9.1i。新版本專門為滿足業界當前面臨的主要設計挑戰而最佳化，這些挑戰包括時序收斂、設計人員生產力和設計功耗。除了運行速度提高2.5倍以外，ISE 9.1i還新採用了SmartCompile 技術，因而可在確保設計中未變更部分實施結果的同時，將硬體實現的速度再提高多達6倍。同時，ISE 9.1i 還最佳化了其最新65nm Virtex™-5 平台獨特的ExpressFabric™技術，可提供比競爭對手的解決方案平均高出30%的性能指標。對於功耗敏感的套用， ISE 9.1i還可將動態功耗平均降低10%。
這一革命性的技術得益於賽靈思Synplicity超高容量時序收斂工作組（Xilinx-Synplicity Ultra High-Capacity Timing Closure Task Force）的工作成果。 該技術提供了業界領先的生產力提升能力，可保證最快的時序收斂路徑，並且最佳化了賽靈思領先的Virtex™ 系列和Spartan™-3 新一代 FPGA器件產品的功耗和性能。
“對於少許設計更改來說，特別是在設計周期的後期，快速的設計實施速度和可預測的時序結果極為重要。”領先的定製汽車系統供應商德國Harmon/Becker 汽車系統有限公司負責製圖平台的高級技術專家Jochen Frensch說：“對於較小的設計變更，XST (Xilinx Synthesis Technology) 的綜合技術可保留設計未改變部分的名稱，而SmartGuide技術在實施過程中可保持高達99%的設計實現不變，因此我們可以發現實施的運行速度越來越快。ISE 9.1i中新採用的SmartGuide技術提供了巨大的優勢。”
ISE 9.1i 提供：
性能 - 比現有競爭解決方案平均快 30%
生產率 - 推出了新 SmartCompile 技術
功耗 - 動態功耗平均降低 10%
性能
比現有競爭解決方案平均快 30%
ISE 9.1i 仍居於性能領先地位。
無需進行布局規劃即可實現時序收斂
*改善的預布線延遲估計使得上游工具能夠最佳化真正的關鍵路徑。
*利用 Virtex™-5 對角互聯來實現延遲最佳化
*支持 6 LUT，從而改善了性能、功耗和利用率
*減少 LUT 數量 → 減少布線和邏輯電平 → 提高性能和降低功耗
*物理綜合最佳化
ISE 9.1i 設計工具內的特性基於 ISE Fmax 技術的性能，專門用於為基於 Virtex-5 的、高密度、高性能設計提供無可比擬的性能和時序收斂結果。 ISE 9.1i 集成式時序收斂流程整合了增強型物理綜合最佳化，提供了最佳的時鐘布局、更好的封裝和時序收斂映射，從而獲得了更高質量的結果。
最佳布線算法能夠有效地利用 65nm ExpressFabric™ 的對角對稱互聯，從而將延遲降至最低水平，和充分利用 Virtex-5 平台的高性能特性。 根據時序要求，ISE 9.1i 布線算法還支持引腳交換，從而可以將設計性能進一步最大化。
整個 ISE 9.1i 基礎設施是一個擴展的時序收斂環境 - 虛擬“時序收斂平台（Timing Closure Cockpit）” - 實現了約束輸入、時序分析、布局規劃和報告視窗之間的無縫交叉探測，因此設計者能夠更輕鬆的完成時序問題分析。
生產率
推出了新 SmartCompile 技術
映射、布局和布線算法的改善能夠讓用戶將棘手的設計的編譯次數平均加快2.5倍。 這讓用戶能夠從他們的設計中獲得更多的實現或回報，從而加快了面市，並減少了失敗。
利用 ISE 9.1i 內的新 SmartCompile 技術，FPGA 設計者可以將運行時間平均加快 2.5 倍，而某些設計甚至可以將運行時間加快 6 倍。
SmartCompile 由 3 種新特性組成：SmartGuide、分區和 SmartPreview。
分區可以保證保留現有實現。 用戶可以在其設計中定義分區或分級模組。 他們能夠規定重新實現過程中要保留這些分區的綜合、布局和/或布線。
SmartGuide 將相同設計不同版本之間的實現差異降至最低水平。 SmartGuide 由 ISE 項目瀏覽器（Project Navigator）提供，並且無需對現有設計流程做大量修改。可以加快運行時間，並且還能為不在關鍵路徑上的小的設計修改保留時序。
SmartPreview 允許用戶暫停和恢復實現。 這使得用戶能夠保存中間結果，查看設計狀態（時序失敗的路徑、布線狀態），生成比特流，並進行時序分析。 通過研究實現過程，這可以降低長實現周期的影響。
其他信息
ISE 9.1i 包含其它一些有助於設計者快速實現時序收斂的新性能，包括：
*新的 Tcl 命令視窗：新的 Tcl 視窗讓用戶能夠在 ISE 圖形環境和命令行之間輕鬆實現導航。
*原始碼控制性能：使得用戶能夠快速而又輕鬆地識別與其設計的已知版本相關的檔案。 然後，他們可以導出重新生成具有*相同源和設定的項目所需的源檔案與腳本。
*集成式時序收斂環境：在 ISE 9.1i 中對集成式時序收斂環境進行了擴展。 PACE、時序分析器、約束編輯器和布局規劃器視窗的整合實現了這些視窗與 ISE 設計總結之間的交叉探測。 這使得用戶能夠從多個角度研究其設計和地址問題。 集成式時序收斂環境可用於 Virtex-5、Virtex-4 和 Spartan™-3A 器件。
功耗
動態功耗平均降低 10%
*先進的綜合和實現算法將動態功耗降低了10%
*免費的、可下載的、領先的 Xilinx FPGA 的 XPower 估計器電子數據表讓用戶能夠利用器件專用電子數據表工具快速而輕鬆地估計其項目的功耗。
*XPower 分析器包含 ISE 的所有配置，可以執行詳細的基於設計的功耗分析，包括導入詳細的設計精度方面的仿真檔案。
*在 Xilinx 功耗中心，找到與功耗有關的問題
Xilinx 9.1i Packs New Capabilities
For system designers, Moore’s Law is a gravy train. Every couple of years, you get more gates, more speed, less power consumption, and lower cost. For digital designers and tool developers, however, that gravy train is headed through the tunnel right at you. Every couple of years, you have more gates to design in less time, more complexity to overcome, and tougher verification problems. Your design tools are heavily impacted, too. The old synthesis and place-and-route runs that took a few minutes on an old 200MHz Windows 98 laptop are now running for 24 hours on the latest multi-core, memory-laden, tricked-out machines.
Xilinx’s latest software release goes straight at that problem, acknowledging that in this day of platform-based design, IP re-use, hardware/software verification, and high-speed serial I/O, the toughest FPGA design challenge for most people is still basic timing closure from RTL to bitstream. Xilinx’s new ISE 9.1i includes two major enhancements: “SmartCompile,” to address timing closure on large designs, and some new power optimization capabilities to address the growing sensitivity to power consumption in today’s more FPGA-centric systems.
Xilinx tackled the runtime and productivity issue both in evolutionary progress on runtimes and algorithm efficiency (boosted by faster computing platforms, of course) and in more revolutionary change in the form of incremental design capability.
Before tackling incrementality, Xilinx claims to have achieved a 2.5X average improvement in runtime. Since we here in Journal land always hate “2.5X faster” as a way of talking about runtime improvements – here is what that means, according to our super-secret “execution speed” decoder ring: the runtime would be divided by 2.5, giving a 60% runtime reduction. Xilinx measures runtime over a suite of 100 “typical” customer designs on the same machine running the old and new versions of the software, then averages the deltas. Voila! 60% runtime reduction on average – “2.5X faster” (Ain’t marketing wonderful?) Actually, a 60% reduction is monumental in software performance tuning… particularly on a product whose release number is in the 9.X range. Normally, the easy speed gains are back in releases 1.x, 2.x etc. when you’ve got plenty of stupid n-squared loop issues to clean up. Mature software has much less low-hanging fruit.
Since most design (particularly the timing closure phase) involves iterative running of steps like synthesis and place-and-route, efficient, intelligent incremental design tools can effect a dramatic improvement in average iteration time. If you go into your design and change only one small section, you don’t want to wait around while all the other parts of your design are re-compiled exactly as they were before. You’d like for just the new and changed sections to require recompilation.
All this incrementality sounds great in concept, of course. It’s in the real-world implementation that problems crop up. That’s where Xilinx has had to focus their energy in providing practical incremental design. The classic difficulties in incremental compilation include things like sub-optimal timing results caused by modified parts of the design introducing new critical timing paths, some of which could benefit from a re-placement or re-synthesis of untouched design blocks. Additionally, sometimes you have to rip up or move existing sections of a design to make way for the new, larger, or otherwise different modified sections. Managing this squishy situation is one of the core challenges of incremental design tools. Another challenge is overhead management. Often, the compute and storage overhead required to provide incremental design capability can cause slowdowns and inefficiencies that eat up the speed gains that incrementality is intended to provide.
Xilinx claims to have addressed these issues in developing their new “SmartCompile” technology. When you’ve already run your design once, you can make minor changes without requiring the software to do a complete re-implementation of the design from scratch. Besides improving runtimes, this locks down the timing on parts of the design where you’ve already completed timing closure – the old non-incremental process could sometimes blow the results from one section of the design while processing changes in another. Preserving the old results as much as possible between incremental iterations helps speed convergence. Overall, Xilinx claims another “2.5X speedup” from incrementality on subsequent runs. By our decoder-ring math again – that means that you might save an average of 84% runtime on an incremental run with the new release versus a full run with the old release. Xilinx calls this a “6.25X faster” runtime.
Xilinx has also added a feature called “SmartPreview” that allows place-and-route to “pause” and “resume” – this allows you to view intermediate results without waiting for the whole run – a big time saver if you discover something that’s wrong early on instead of waiting for an overnighter to complete. The SmartPreview allows you to create a bitstream to take into a part immediately for debug, preserve your latest results as a snapshot, abort the place-and-route process entirely, or move to the next run of a multi-pass place-and-route process.
Finally, the new “SmartCompile” boasts a feature called “SmartGuide” that attempts to minimize the change between iterations, reducing the timing perturbation and runtimes for small design changes of the type usually encountered late in the design cycle. SmartGuide is a pushbutton algorithm that compares the new and old versions of a design, uses the original design as a guide, and incrementally places the new or changed elements and critical elements. It then identifies critical timing paths and incrementally routes new and critical paths to meet timing in order to reach a final implementation. Furthermore, you can manually identify partitions if you want to exercise more control, which is particularly useful for situations like team-based design where multiple engineers may be working on a single FPGA and be at different phases of their own implementation.
Xilinx has thrown a few more convenience and productivity features into the release, including a TcL console to allow scripting, the hooks necessary to integrate a variety of source code management systems into your design flow with ISE, and an expanded timing closure environment that brings together the various timing closure tools into one user interface.
The second major challenge tackled by the new ISE is power optimization. Power in FPGA designs is only recently becoming a first-class concern. Old FPGA users just took whatever power consumption they got, plugged in bigger power supplies and fans if needed, and took it all as an excuse for the occasional marshmallow roast over their development boards. Today, however, many designers actually care how much power their FPGA design will burn. FPGAs are becoming more central to the system, larger, and faster. All of those factors make them higher on the most-scrutinized components list for suspicion of power mongering.
First on Xilinx’s list of chores was to improve the accuracy and timeliness of power estimation. Many design projects have ended up far down the implementation trail only to discover that they were impossibly far over their power budget. Early estimation is the only way to get confidence that you’re headed toward a workable solution from a power perspective. Xilinx has included new power estimation spreadsheets into ISE that help you get a rough idea of the power picture early on.
Once you get into your design process, you want to cut power consumption as much as possible. Xilinx has added new power optimization in both synthesis and place-and-route that they claim automatically reduces dynamic power by an average of 10%. Power consumption is highly design- and stimulus-dependent, however, so don’t be surprised if you see a wide variation in your results.
