霍宗亮

霍宗亮，2003.9–2010.2韓國三星電子公司三星半導體研發中心。

基本介紹

• 中文名：霍宗亮
• 國籍：中國
• 民族：漢族
• 主要成就：新型半導體存儲技術

個人信息

霍宗亮，研究員。

教育背景

1994-09--2003-07 北京大學 本、碩、博士學位

工作經歷

工作簡歷

2010-03~現在, 中科院微電子研究所, 研究員

2003-09~2010-02,韓國.三星半導體研發中心, 高級工程師

研究方向

新型半導體存儲技術

專利與獎勵

獎勵信息

（1） 積體電路產業技術創新戰略聯盟技術創新獎, 其他, 2019

（2） 積體電路產業技術創新戰略聯盟技術創新獎, , 其他, 2018

（3） 2017年度中國科學院微電子研究所科研成果一等獎, 研究所（學校）, 2017

（4） 2017年度中國科學院微電子研究所研究生喜愛的導師, 研究所（學校）, 2017

（5） 2016年度中國科學院微電子研究所顯著科研進展, 研究所（學校）, 2016

（6） 2016年度中國科學院微電子研究所研究生喜愛的導師, 研究所（學校）, 2016

（7） 22納米積體電路核心工藝技術及套用, 一等獎, 市地級, 2016

（8） 2015年度中國科學院微電子研究所研究生喜愛的導師, 研究所（學校）, 2015

（9） 2015年度中國科學院微電子研究所科研成果獎一等獎, 一等獎, 研究所（學校）, 2015

（10） 2015年度中國科學院“***計畫”終期評估優秀, , 院級, 2015

（11） 2014年度中國科學院傑出科技成果獎, 院級, 2014

出版信息

發表論文

（1） Impact of Cycling Induced Intercell Trapped Charge on Retention Charge Loss in 3-D NAND Flash Memory[J], IEEE Journal of the Electron Devices Society,, 2020, 通訊作者

（2） Influence of accumulated charges on deep trench etch process in 3D NAND memory[J], Semiconductor Science and Technology, 2020, 通訊作者

（3） Analysis and Optimization of Threshold Voltage Variability by Polysilicon Grain Size Simulation in 3D NAND Flash Memory [J], IEEE Journal of the Electron Devices Society, 2020, 通訊作者

（4） Optimization of Performance and Reliability in 3D NAND Flash Memory [J], IEEE Electron Device Letters, 2020, 通訊作者

（5） . A novel solution to improve saddle-shape warpage in 3D NAND flash memory[J], Semiconductor Science and Technology, 2020, 通訊作者

（6） 一種用於三維快閃記憶體測試的低成本PMU電路, 微電子學與計算機, 2020, 通訊作者

（7） 3D NAND快閃記憶體數據保持力與初始狀態依賴性研究[J], 電子學報, 2020, 通訊作者

（8） Multi-Coding ECC Algorithm Based on 3D Charge Trap NAND Flash Hot Region Cell Prediction, IEEE Communications Letters, 2020, 通訊作者

（9） Investigation of Program Noise in Charge Trap Based 3D NAND Flash Memory[J], IEEE Electron Device Letters, 2020, 通訊作者

（10） An Improved Dimensional Measurement Method of Staircase Patterns with Higher Precision in 3D NAND[J], IEEE Access, 2020, 通訊作者

（11） Hydrogen Source and Diffusion Path for Poly-Si Channel Passivation in Xtacking 3D NAND Flash Memory[J], Journal of the Electron Devices Society, 2020, 通訊作者

（12） 三維存儲器技術中高熱預算條件下表面溝道 PMOS開發研究, 微電子學, 2019, 通訊作者

（13） An effective process to remove etch damage prior to selective epitaxial growth in 3D NAND flash memory, Semiconductor Science and Technology, 2019, 通訊作者

（14） Cycling induced Trap Generation and Recovery near the Top Select Gate Transistor in 3D NAND, 2019 IEEE International Reliability Physics Symposium (IRPS), 2019, 通訊作者

（15） Influence of rapid thermal annealing on the wafer warpage in 3D NAND flash memory, Semiconductor Science and Technology, 2019, 通訊作者

（16） Investigation of Threshold Voltage Distribution Temperature Dependence in 3D NAND Flash, IEEE Electron Device Letters, 2019, 通訊作者

（17） Program Voltage Generator with Ultra-Low Ripple for 3D NAND Flash in Standard CMOS Process, 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2019, 通訊作者

（18） 三維快閃記憶體中基於鎢互連的空氣隙結構的製備工藝, 半導體製造技術, 2019, 通訊作者

（19） Investigation of erase cycling induced TSG Vt shift in 3D NAND Flash Memory, IEEE Electron Device Letters, 2019, 通訊作者

（20） 3D NAND Flash的片上控制邏輯電路設計, 微電子學與計算機, 2019, 通訊作者

（21） 適用於3D NAND的高穩定度的capacitor-free LDO, 現代電子技術, 2019, 通訊作者

（22） A High Density and Low Cost Staircase Scheme for 3D NAND Flash Memory: SDS(Stair Divided Scheme), ECS Journal of Solid State Science and Technology, 2019, 通訊作者

（23） The influence of grain boundary interface traps on electrical characteristics of top select gate transistor in 3D NAND flash memory, Solid State Electronics, 2018, 通訊作者

（24） A Novel Program Scheme for Program Disturbance Optimization in 3-D NAND Flash Memory, IEEE Electron Device Letters, 2018, 通訊作者

（25） The Optimization of Gate All Around-L-Shaped Bottom Select Transistor in 3D NAND Flash Memory, Journal of Nanoscience and Nanotechnology, 2018, 通訊作者

（26） Word line interference based data recovery technique for 3D NAND Flash, IEICE Electronics Express, 2018, 通訊作者

（27） A fast read retry method for 3D NAND flash memories using novel valley search algorithm, IEICE Electronics Express, 2018, 通訊作者

（28） Impact of BEOL Film Deposition on Poly-Si 3D NAND Device Characteristics, ICSICT 2018 International Conference on Solid-State and Integrated Circuit Technology, 2018, 通訊作者

（29） Modeling and optimization of array leakage in 3 D NAND flash memory, 2018 IEEE International Conference on Integrated Circuits, Technologies and Applications, 2018, 通訊作者

（30） Investigation of Reducing Bow during High Aspect Ratio Trench Etching in 3D NAND Flash Memory, IEEE 14th International Conference on Solid-State and Integrated-Circuit Technology, 2018, 通訊作者

（31） A 12V Low-ripple and High-Efficiency Charge Pump with Continuous Regulation Scheme for 3D NAND Flash Memories, IEEE 14th International Conference on Solid-State and Integrated-Circuit Technology, 2018, 通訊作者

（32） Investigation of Cycling-Induced Dummy Cell Disturbance in 3D NAND Flash Memory, IEEE ELECTRON DEVICE LETTERS, 2017, 通訊作者

（33） A Novel Read Scheme for Read Disturbance Suppression in 3D NAND Flash Memory, IEEE Electron Device Letters, 2017, 通訊作者

（34） Leakage Characterization of Top Select Transistor for Program Disturbance Optimization in 3D NAND Flash, Solid State Electronics, 2017, 通訊作者

（35） A 1.2mV ripple, 4.5V charge pump using controllable pumping current technology, IEICE Electronics Express, 2017, 通訊作者

（36） Dynamic LLR scheme based on EM algorithm for LDPC decoding in NAND flash memory, IEICE Electronics Express, 2017, 通訊作者

（37） A high efficiency all-PMOS charge pump for 3D NAND flash memory, Journal of Semiconductors, 2016, 通訊作者

（38） Investigation of tunneling layer and inter-gate-dielectric engineered TaN floating gate memory, Integrated Ferroelectrics, 2016, 通訊作者

（39） Impact of Critical Geometry Dimension on Channel Boosting Potential in 3D NAND Memory, 2016 IEEE 13th International Conference on Solid-State and Integrated Circuit Technology, 2016, 通訊作者

（40） Simulation On Threshold Voltage Of L-Shaped Bottom Select Transistor In 3D NANDFlash Memory, 2016 IEEE 13th International Conference on Solid-State and Integrated Circuit Technology, 2016, 通訊作者

（41） String Select Transistor Leakage Suppression By Threshold Voltage Modulation In 3DNAND Flash Memory, 2016 IEEE 13th International Conference on Solid-State and Integrated Circuit Technology, 2016, 通訊作者

（42） Performance Enhancement of Metal Floating Gate Memory By Using a Bandgap Engineered High-k Tunneling Barrier, Ecs Transactions, 2016, 通訊作者

（43） Low temperature post deposition annealing investigation for 3D charge trap flash memory by Kelvin probe force microscopy, Applied physics A, 2015, 第 1 作者

（44） Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors, scientific reports, 2015, 通訊作者

（45） Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory, Journal of Semiconductors, 2015, 通訊作者

（46） A write buffer design based on stable and area-saving embedded SRAM for flash applications, Science China Technological Sciences, 2015, 通訊作者

（47） Gate Bias Dependence of Complex Random Telegraph Noise Behavior in 65-nm NOR Flash Memory, IEEE Electron Device Letters, 2015, 通訊作者

（48） Low temperature atomic layer deposited HfO2 film for high performance charge trapping flash memory application, Semiconductor Science and Technology, 2014, 第 2 作者

（49） A Write buffer based on stable and area saving embedded SRAM for flash applications, Science China, 2014, 第 2 作者

（50） A 65-nm 1-Gb NOR floating-gate flash memory with less than 50-ns access time, Chin. Sci. Bull, 2014, 第 2 作者

（51） Effect of Pre-annealing to Blocking Oxide on the Performance of Dual Trappinglayer Engineered Charge Trapping Memory, Integrated Ferroelectrics, 2014, 第 2 作者

（52） Comparison of N2 and O2 anneal on the integrity of Al2O3/Si3N4/SiO2/Si memory gate stack, Chinese Physics B, 2014, 第 4 作者

（53） Investigation of charge loss characteristics of HfO2 annealed in N2 or O2 ambient, Chinese Journal of Semiconductors, 2014, 第 2 作者

（54） Investigation of HfAlO trapping layer with various Al contents by variable temperature Kelvin probe force microscopy, ECS Transactions, 2014, 第 2 作者

（55） A Study of P/E Cycling Impaction on Drain Disturb for 65nm NOR Flash Memories by Low Frequency Noise Analyze, Integrated Ferroelectrics: An International, 2014, 第 2 作者

（56） Metal Floating Gate Memory Device With SiO2/HfO2 Dual-Layer as Engineered Tunneling Barrier, Electron Device Letters, 2014, 第 2 作者

（57） A simple and accurate method to measure program/erase speed in a memory capacitor structure, Chin. Phys. B, 2013, 第 3 作者

（58） Investigation of Charge Loss Mechanism of Thickness-Scalable Trapping Layer by Variable Temperature Kelvin Probe Force Microscopy, IEEE ELECTRON DEVICE LETTERS, 2013, 第 2 作者

（59） In situ electron holography study of charge distribution in high-κ charge -trapping memory, Nature, 2013, 第 3 作者

（60） Effect of Damage in Source and drain on the endurance of a 65-nm-node NOR flash memory, IEEE Transactions on Electron Devices, 2013, 第 3 作者

（61） Visualization on Charge Distribution Behavior in Thickness-Scalable HfO2 Trapping Layer by In-situ Electron Holography and, International memory workshop (IMW 2013), 2013, 第 2 作者

（62） Optimization of HfO2 growth process by atomic layer deposition (ALD) for high performance charge trapping Flash memory application, Ecs Transactions, 2013, 第 2 作者

（63） Process Optimization Of HfAlO Trapping Layer For High Performance Charge Trap Flash Memory Application, Ecs Transactions, 2013, 第 2 作者

（64） Charge Loss Characteristics of Different Al Contents in a HfAlO Trapping Layer Investigated by Variable Temperature, Chinese Physics Letters, 2013, 第 2 作者

（65） Effects of Interfacial Fluorination on Performance Enhancement of High-k-Based Charge Trap Flash Memory, JAPANESE JOURNAL OF APPLIED PHYSICS, 2013, 第 2 作者

（66） Isolated nanographene crystals for nano-floating gate in charge trapping memory, SCI, 2013, 第 4 作者

（67） 能帶工程在電荷俘獲存儲器性能和可靠性中的角色 , Effect of bandgap engineering on theperformance and reliability of a high-kbased nanoscale charge trap flash memory, J. Phys. D: Appl. Phys., 2012, 第 3 作者

（68） MANOS結構中高溫退火效應研究, Effect of high temperature annealing on the performance of MANOS charge trapping memory, Science China-Technological Sciences, 2012, 第 3 作者

（69） 基於電容和電流測量的矽納米晶存儲器缺陷產生行為分析, Analyzing Trap Generation in Silicon-Nanocrystal Memory Devices Using Capacitance and Current Measurement, SCIENCE CHINA Technological Sciences, 2012, 第 4 作者

（70） Cycling-Induced Peak-Like Interface State Generation in Si-Nanocrystal Memory Devices, IEEE Electron Device Letters, 2012, 第 3 作者

（71） Comparison of tunneling current assisted by neutral and positive traps with finite ranged core-potential, Journal of Appl. Physics, 2012, 第 3 作者

（72） 基於芯殼結構的納米晶存儲器, Improved performance of non-volatile memory with Au-Al2O3 core-shell nanocrystals embedded in HfO2 matrix, Appl. Phys. Lett. , 2012, 第 3 作者

（73） MANOS結構中阻擋層高溫氧退火效應研究, Effects of high-temperature O2 annealing on Al2O3 blocking layer and Al2O3/Si3N4 interface for MANOS structures , J. Phys. D: Appl. Phys. , 2012, 第 3 作者

（74） Analysis of Cycling Induced Interface Degradation In Si Nanocrystal Memory Devices, Ecs Transactions, 2012, 第 3 作者

（75） 多聲子陷阱輔助隧穿機制的統一模型研究, Unification of three multiphonon trap-assisted tunneling mechanisms, JOURNAL OF APPLIED PHYSICS, 2011, 第 2 作者

（76） 採用EFM對高K電荷俘獲存儲器界面相關的俘獲與損失特性研究, Investigation on interface related charge trap and loss characteristics of high-k based trapping structures by electrostatic force microscopy, Appl. Phys. Lett, 2011, 第 3 作者

（77） 用於高溫套用的鋁納米晶存儲器研究, Performance-improved nonvolatile memory with aluminum nanocrystals embedded in Al2O3 for high temperature applications, JOURNAL OF APPLIED PHYSICS , 2011, 第 2 作者

（78） 採用AlO/HfSiO雙層阻擋層結構的電荷俘獲存儲器研究, Improved charge trapping flash device with Al2O3/HfSiO stack as blocking layer, Chinese Phys. B, 2011, 第 2 作者

（79） 一種用於矽納米晶存儲器的結輔助編程新方法, A Novel Junction Assisted Programming Scheme for Si- Nanocrystal Memory Devices with Improved Performance, Semicond. Sci. Technol, 2011, 第 2 作者

（80） 基於HfO/TaO雙層存儲結構的電荷俘獲存儲器研究, Improved speed and data retention characteristics in flash memory using a stacked HfO2/Ta2O5 charge-trapping layer, Semicond. Sci. Technol, 2011, 第 2 作者

（81） 矽納米晶存儲器中擦寫引起的缺陷產生機制分析, Analysis of Trap Generation during Programming/Erasing Cycling in Silicon Nanocrystal Memory Devices, Semiconductor Science and technology, 2011, 第 4 作者

（82） 石墨烯邊緣氫化用於DNA測序增強, Enhanced DNA sequencing performance through edge- hydrogenation of graphene electrodes, Adv. Funct. Mater., 2011, 通訊作者

（83） 納米晶存儲器多次擦寫引起的退化機理研究, A Study of Cycling Induced Degradation Mechanisms in Si nano-crystal Memory Devices, Nanotechnology, 2011, 第 3 作者

（84） Investigation on interface related charge trap and loss characteristics of high-k based trapping structures by electrostaticforce microscopy, Applied Physics Letters, 2011, 第 3 作者

（85） Optimization of Silicon Nanocrystals Growth Process by LPCVD for Non-Volatile Memory Application, Thin Solid Films, 2011, 第 2 作者

（86） A novel 2-T structure memory device using a Si nanodot for embedded application, J. Semicond, 2011, 第 4 作者

（87） Material properties and effective work function of reactive sputtered TaN gate electrodes, J. Semicond, 2011, 第 2 作者

（88） 基於存儲層能帶調製概念實現多態快閃記憶體器件的性能增強, Performance enhancement of multi-level cell nonvolatile memory by using a band-gap engineered high-к trapping layer , Applied Physics Letters , 2010, 第 2 作者

（89） Performance enhancement of multi-level cell nonvolatile memory by using a bandgap engineered high-k trapping layer, Applied Physics Letters, 2010, 第 2 作者

（90） 利用金屬納米晶實現的阻變存儲器中納米導電細絲的可控生長, Controllable Growth of Nanoscale Conductive Filaments in Solid-Electrolyte -Based ReRAM by Using a Metal, ACS Nano, 2010, 通訊作者

（91） 一種實現納米晶性能增強的結輔助編程新方法, Performance Improvement of Si-NC Memory Device by Using a Novel Junction Assisted Programming Scheme, ECS Transaction, 2010, 第 2 作者

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科研活動

參與會議

（1）A High Efficiency All -PMOS Charge Pump for 3D NAND Flash Memory 2015-11-03

（2）A Novel Adaptive CMOS Low-dropout Regulator with 3A Sink/Source Capability 2015-11-03

（3）Investigation of charge loss mechanisms in 3D TANOS cylindrical junction-less charge trapping memory 2014-10-28

（4）Modeling and analizing of chip level circuit design for 3D-Stackable NAND flash memory 2014-10-28

（5）A page buffer design based on stable and Area-saving embedden sram for flash applications 2014-10-28

（6） Program charge effect on random telegraph noise behavior in multi-level floating gate flash memory 2014-10-28

（7）Cauterization of total ionizing dose effect investigated by in-situ measurements for a 65nm flash technology 2014-10-28

（8）An simple approach to evaluate TID response in high voltage MOSFET for 65nm flash technology 2014-10-28

（9）Performance improvement for Metal/Al2O3/HfO2 / SiO2 /Si structure nonvolatile flash memory by fluorine plasma treatment 2012-10-29

（10）HighPerformance MAHAHOS Memory Devices--Charge Trapping and Distribution in Bandgap Engineered Structure 2012-05-20

（11）Charge trapping and distribution in storage structure: Investigation of bandgap engineered high-k based memory device 2012-05-20

（12）Improved Performance of Nanocrystal Memory Embedded with Au-Al2O3 Core-shell Nanoparticles, 2012-04-10

（13）Reducing Formation Time of the Inversion Layer by Illumination around a Memory Capacitor 2012-03-18

（14）Investigation of charge trapping and loss characteristics for charge trap flash memory by electrostatic force microscopy 2011-11-07

（15）Investigation of charge trapping and loss characteristics for charge trap flash memory by electrostatic force microscopy 2011-11-07

（16）Performance optimization for TANOS by using pre-treatment of plasma oxygenic ions 2011-11-07

（17）Performance optimization for MANOS by using pre-treatment of plasma oxygenic ions 2011-07-31

（18）Bandgap engineered HfO2/Al2O3/HfO2 trapping layer for high-performance charge trap memory 2011-06-12

（19）Novel MAHOS-type flash memory using different charge trapping layers 2011-06-12

（20）Stacked high-k charge trapping layer for high performance flash memory application 2011-03-13

（21）Performance Improvement of Si-NC memory device by using a novel programming scheme 2011-03-13

（22）Pre-cycling with higher voltages for endurance improvement of silicon nanocrystal memory device 2010-11-01

（23）Improved Performance of Si-NC Memory Using a Novel Two-Step Program Scheme 2010-11-01