在業界著名國內外期刊IEEE Electron Device Letters, IEEE TRANSACTIONS ON ELECTRON EVICES,Solid-State Electronics和半導體學報以及國際會議上發表和錄用學術論文近30篇,其中14篇SCI檢索,所有文章均被EI檢索,申請中國專利9個,4個已授權。
因在半導體器件領域取得的較突出的研究成果,被邀為微電子器件領域國際最具影響力的期刊IEEE Electron Device Lett., IEEE Tran. Electron Devices 和Solid-State Electronics的審稿人,並藉此可了解國際微電子器件領域發展動態。
學術成果
代表性學術成果(部分):
(一)學術論文
行業頂級期刊IEEE EDL和IEEE TED共14篇
[1]Xiaorong Luo, Y H Jiang, K Zhou, Bo Zhang et al. Ultra-low Specific On-Resistance Superjunction Vertical
DMOS with High-K Dielectric Pillar,IEEE Electron Device Lett., 33(7) ,1042-1044, 2012.
[2]Xiaorong Luo, J Fan, Bo Zhang Florin Udrea, Ultra-low Specific On-Resistance High Voltage SOI Lateral
MOSFET,IEEE Electron Device Lett., 32(2), 185-187, 2011.
[3]Xiaorong Luo, Yuangang Wang, Guoliang Yao, et al, High Voltage Partial SOI LDMOS with a Variable Low-k Dielectric Buried Layer and a Buried P-layer,IEEE Electron Device Lett., 31(6), 594-596, 2010.
[4]Xiaorong Luo, Tianfei Lei, Bo Zhang, et al. A high-voltage LDMOS compatible with high voltage integrated
circuits on p-type SOI layer,IEEE Electron Device Lett., 30 (10), 1093-1095, 2009.
[5]Xiaorong Luo, Zhaoji Li, Bo Zhang, et al. Realization of High Voltage ( >700V) in New SOI Devices with a
Compound Buried-Layer,IEEE Electron Device Lett., 29(12), pp.1395-1397, 2008.
[6]Xiaorong Luo, Bo Zhang, Zhaoji Li, et al. A Novel 700-V SOI LDMOS with Double-Sided Trench,IEEE
ElectronDevice Lett., 28(5): 422-424, 2007.
[7]Xiaorong LuoJie Wei,Xianlong Shi,Kun Zhou,Ruichao Tian,Zhaoji Li,Bo Zhang ,Novel Reduced ON-Resistance LDMOS With an Enhanced Breakdown Voltage,IEEE Trans. on Electron Devices, 2014,
61(12):4304-4308.
[8]Xiaorong Luo, J Y Cai, Y Fan,et al. Novel Low-Resistance Current path UMOS with High-K Dielectric Pillars,
IEEE Trans. Electron Devices, 60(9), 2840-2846, 2013.
[9] Xiaorong Luo, T F Lei, Y. G. Wang. Low On-Resistance SOI Dual Trench- Gates MOSFET,IEEE Trans. on
ElectronDevices, 59(2), 504-509, 2012.
[10]Xiaorong Luo, H Deng, Y G Wang, Novel Low-k Dielectric Buried Layer High Voltage LDMOS on Partial
SOI,IEEE Tran. Electron Devices, 57(2), pp.535-538, 2010.
[11]Xiaorong Luo, Bo Zhang, Tianfei Lei, Florin Udrea, et al, Numerical and Experimental Investigation on a
Novel High Voltage SOI LDMOS in the self- isolation HVIC,IEEE Tran. Electron Devices, 57(11), pp. 3033-
3043, 2010.
[12]Xiaorong Luo, Daping Fu, Lei Lei et al. Eliminating Back-Gate Bias Effects in a Novel SOI High-Voltage
Device Structure,IEEE Tran. Electron Devices, 56(8), pp.1659-1666, 2009.
[13]Xiaorong Luo, Bo Zhang, Zhaoji Li. New high voltage (>1200V) MOSFET with the chargeTrenches on
Partial SOI,IEEE Tran. Electron Devices,2008, 55(7), 1756-1761.
[14]Xiaorong Luo,Qiao Tan,Jie Wei,Kun Zhou,Gaoqiang Deng,Zhaoji,Ultralow On-Resistance High
Voltage p-channel LDMOS with anAccumulation-Effect Extended Gate,IEEE Transactions on Electron
Devices,63(6), p.2614,2016.
[15]Xiaorong Luo*, Da Ma,Jie Wei , et al.A split gate power FINFET withimproved on-resistance
andswitching performance,IEEE Electron Device Lett., 37(9), p.1185,2016.
[16]Xiaorong Luo*, Mengshan Lv, et al.Ultralow On-Resistance SOI LDMOSwith Three Separated Gates and
[17] Kun Zhou,Xiaorong Luo*, Qing Xu, et al. A RESURF-Enhanced P-Channel SOI LDMOS with Ultralow
Specific On-Resistance,IEEE Tran. Electron Devices, 61(7),2466 - 2472, 2014.
[18]Jie Wei ,Xiaorong Luo*,Yanhui Zhang,Pengcheng Li,Kun Zhou,BoZhang,Zhaoji Li,High Voltage
Thin SOI LDMOS with Ultralow On-resistance andEvenTemperature Characteristic,IEEE Transactions on
Electron Devices,63(4),p.1637,2016.
[19] Kun Zhou,Xiaorong Luo*, Qing Xu, et al.Analytical Model and New Structureof the Variable-k Dielectric
Trench LDMOS with Improved,IEEE Transactions on ElectronDevices,62(10), p.3334, 2015.
[20] Kun Zhou,Xiaorong Luo*, Linhua Huang, et al.,An Ultralow Loss Superjunction Reverse Blocking Insulated-
Gate Bipolar Transistor with Shorted-Collector Trenchaccepted, 2016
[21]Luo Xiao-Rong, Wang Yuan-Gang, Deng Hao, and Florin Udrea, A Novel Partial Silicon-On-Insulator High
Voltage LDMOS with Low-k Dielectric Buried Layer, Chinese Physics B, 19(7), 077306-1-6, 2010.
[22]Luo Xiao-Rong, Yao Guo-liang, Wang Yuan-Gang, et al.Ultra-low On-Resistance High Voltage (>600) SOI MOSFET with a Reduced Cell Pitch, Chinese Physics B, 20(2): 028501, 2011.
[23] Shi Xian-Long,Luo Xiao-Rong*(通信作者),Wei Jie,Tan Qiao ,A novel LDMOS with a junction field