王伶俐(復旦大學教授)

王伶俐(復旦大學教授)

王伶俐,英國愛丁堡Napier大學博士,教授,博士生導師,IEEE會員,上海市浦江人才,IEEE Council on Electronic Design Automation (CEDA) Shanghai Chapter主席,復旦大學微電子學院EDA研究所副所長。

基本介紹

  • 中文名:王伶俐
  • 職業:復旦大學教授
  • 畢業院校:浙江大學
  • 性別:男
  • 學歷:博士
人物簡介,工作背景,研究領域,主要項目,主要論文,

人物簡介

1990年畢業於浙江大學西溪校區物理系,後留校工作。1997年畢業於浙江大學電子工程系電路與系統專業,獲工學碩士學位。2000年底在英國愛丁堡 Napier大學工程學院獲博士學位。出國前曾講授浙江大學電子工程系研究生課程。
博士畢業後在可程式晶片(FPGA)供應商Altera公司歐洲技術中心研發部工作4年多。2005年4月人才引進到復旦大學專用積體電路與系統國家重點實驗室工作。共發表學術論文100餘篇,其中被SCI/EI檢索80餘篇。擁有美國授權專利一項,中國發明專利授權六項、實用新型授權專利一項、計算機軟體著作權一項。2010年至2013年擔任“新型計算結構與產業技術創新戰略聯盟”首屆專家委員會成員和863重點項目“新概念高性能計算機體系結構及系統研究開發”總體組專家。2014年至今擔任International Conference on Field Programmable Technology國際會議指導委員會成員(steering committee member)。

工作背景

在可程式晶片供應商Altera公司歐洲技術中心研發部工作4年多, 從事於Quartus軟體, Excalibur系列產品 (內嵌ARM微處理器和存儲器的系統級可程式晶片), Nios通用嵌入式 RISC微處理器, 和HardCopy(從FPGA到 ASIC) Structured ASIC成套工具的研發與調試。熟悉硬體和軟體以及 SoC/SOPC (System-On-a-Programmable-Chip) 系統的開發與套用。
回國後主要從事FPGA軟硬體系統的教學、研究和套用。承擔大二的基礎課程“計算機軟體基礎”,開設全英語教學的本科生選修課程“FPGA結構原理和套用” (2016年起獲“復旦大學優秀全英語課程”)、碩士研究生學位專業課程“系統級可程式晶片設計”和博士研究生選修課程“可程式邏輯器件原理和CAD”與“數字積體電路設計中的高級綜合技術”。2007-2008年參與了瑞典KTH和復旦大學聯合研究生培養的“嵌入式系統”課程。
在科研方面,主要負責的項目資助來源於美國、加拿大、日本、瑞士公司或大學的國際合作,國家科技重大專項,國家自然科學基金面上項目和重點項目子課題,國家863計畫重點項目子課題,教育部留學回國人員基金,上海市浦江人才計畫,上海市“科技創新行動計畫”,上海市科委白玉蘭人才基金和國內通信公司、金融公司、生物公司和研究所的橫向合作等。主要研究領域包括FPGA積體電路設計、EDA算法、可重構系統及其套用加速和量子計算等。在海量圖像識別或者視頻匹配套用方面,經過863高性能計算機評測中心的第三方測試,相對於2012年IBM主流伺服器X3650,在不同精度、幀聚合度的要求下達到平均220多倍的性能加速和效能提升,驗證了可重構擬態計算機結構的優越性。所參與開發的世界首台擬態計算機被列入2013年中國十大科技進展新聞。2008年11月至12月,作為Visiting Faculty在美國Cadence Research Lab at Berkeley進行基於LUT的工藝映射合作研究工作。2010年7月至8月,在荷蘭TUDelft和瑞士EPFL兩所大學從事新型可程式邏輯結構的國際合作研究。近幾年開展的國際合作交流學者來源於UC Berkeley、UCLA、UCR、多倫多大學、Imperial College和澳大利亞的悉尼大學等。

研究領域

l 大規模數字積體電路面積,功耗,可測試性,和可布線性(routability)的最佳化。
l 面向可程式晶片(CPLD & FPGA)的EDA軟體開發與套用。
l 軟/硬體協同設計(SW/HW co-design) 。
l High-Level Synthesis最佳化算法。
l 嵌入式SoC/SOPC系統的開發與套用,特別是計算複雜,並行性和實時性要求高的套用場合。
l 面向Reconfigurable Computing的可程式晶片結構研究。
l 量子計算的電路設計最佳化。

主要項目

  1. 美國Synopsys公司,“FPGA晶片設計和軟體系統”,負責FPGA軟體系統的開發,2005.2 – 2007.2
  2. 智銳電子系統設計(上海)有限公司,“面向可重構計算的FPGA軟體算法開發”,負責人,2006.10 – 2007.3
  3. 國家自然科學基金面上項目,“量子計算電路的設計和綜合”, 負責人,2007.1-2009.12
  4. 教育部留學回國人員科研啟動基金,“量子計算電路的設計和最佳化”, 負責人,2008.3
  5. 上海市浦江人才項目,“抗輻射FPGA硬體電路與軟體最佳化算法研究”, 負責人,2008.9-2010.9
  6. 上海市“科技創新行動計畫”積體電路設計專項,“國產自主智慧財產權FPGA的產業化套用和深入研發”, 負責FPGA軟體系統的開發,2008.10-2010.9
  7. Sino-Swiss Science and Technology Cooperation 2008-2011(中瑞科技合作計畫),“Programmability Implementation Using Plasmonics Based on the MBQC Framework”,2009.8 – 2010.9
  8. Canada-China Scientific and Technological Cooperation(中國國際人才交流協會和加拿大科學技術合作中心),Organization of International Workshop on Emerging Circuits and Systems, 2009.8-2011.8
  9. “核高基”國家科技重大專項項目,“嵌入式可程式邏輯陣列IP核”, 軟體子課題負責人, 2009.1-2011.6
  10. 國家863計畫重點項目“新概念高效能計算機體系結構及系統研究開發”子課題,“納米尺度SoC精化設計與驗證技術研究”,負責人,2009.9 - 2010.5
  11. 國家863計畫重點項目“新概念高效能計算機體系結構及系統研究開發”子課題,“非馮體系結構研究”,負責人,2009.9 - 2010.1
  12. 上海市科委白玉蘭人才基金,“三維FPGA的熱分析模型研究”, 2009.5 – 2010.5
  13. 國家自然科學基金面上項目,“量子可程式邏輯陣列結構研究”(61171011), 負責人,2012.1-2015.12
  14. 國家自然科學基金重點項目“基於雙邏輯的低功耗IP核設計基礎理論與關鍵技術”子課題“基於雙邏輯IP核的驗證和測試平台”(61131001),子課題負責人,2012.1-2016.12
  15. 國家863計畫重點項目“新概念高效能計算機體系結構及系統研究開發”子課題,“面向圖像識別的HRCA設計與實現”,2011.12 - 2013.9
  16. 國家自然科學基金國際(地區)合作與交流項目,第13屆IEEE現場可程式技術國際會議(FPT2014),2014.9 - 2014.12

主要論文

  1. Jian Yan, Junqi Yuan, Philip H. W. Leong, Wayne Luk, and Lingli Wang, Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
  2. Li Ding, Kang Ping, Wenbo Yin and LingLi Wang, Hardware TCP Offload Engine based on 10-Gbps Ethernet for Low-Latency Network Communication, IEEE International Conference on Field-Programmable Technology (FPT2016), pp.265- 268, 2016
  3. Qi Zhan, Min Gao, Li Jiao, Shiwen Wang, Xitian Fan, Wei Cao, Xuegong Zhou and Lingli Wang, High Performance Deformable Part Model Accelerator Based on FPGA, IEEE International Conference on Field-Programmable Technology (FPT2016), pp.241- 244, 2016
  4. Zhehao Li, Jifang Jin, Ji Yang, Jiahua Lu, Lingli Wang, A Moving Object Extraction and Classification System based on Zynq and IBM SuperVessel, IEEE International Conference on Field-Programmable Technology (FPT2016), pp.303- 306, 2016
  5. Wei Liang, Wenbo Yin, Ping Kang, Lingli Wang, Memory Efficient and High Performance Key-value Store on FPGA Using Cuckoo Hashing, Field-Programmable Logic and Applications (FPL2016), Lausanne, pp.379-382, 2016
  6. Hao Zhou, Xinyu Niu, Junqi Yuan, Lingli Wang, Wayne Luk, Connect On the Fly: Enhancing and Prototyping of Cycle-Reconfigurable Modules, Field-Programmable Logic and Applications (FPL2016), Lausanne, pp.233-240, 2016
  7. Xitian Fan, Huimin Li, Wei Cao, Lingli Wang, DT-CGRA: Dual-Track Coarse-Grained Reconfigurable Architecture for Stream Applications, Field-Programmable Logic and Applications (FPL2016), Lausanne, pp.78-86, 2016
  8. Huimin Li, Xitian Fan, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang, A High Performance FPGA-based Accelerator for Large-Scale Convolutional Neural Networks, Field-Programmable Logic and Applications (FPL2016), Lausanne, pp. 69-77, 2016
  9. Jifang Jin, Jian Yan, Xuegong Zhou and Lingli Wang, An Adaptive Cross-Layer Fault Recovery Solutionfor Reconfigurable SoCs, IEEE International Conference on Field-Programmable Technology (FPT2015), Queenstown, 2015
  10. Jian Yan, Jifang Jin, Ying Wang, Xuegong Zhou, Leong Philip and Lingli Wang, UniStream: A Unified Stream Architecture Combining Configuration and Data Processing, Field-Programmable Logic and Applications (FPL2015), London, 2015
  11. Jian Yan, Junqi Yuan, Ying Wang, Philip Leong and Lingli Wang, Design Space Exploration for FPGA-based Hybrid Multicore Architecture, IEEE International Conference on Field-Programmable Technology (FPT2014), pp.280-281, 2014
  12. Jiasen Huang, Junyan Ren, Wenbo Yin and Lingli Wang, No Zero Padded Sparse Matrix-Vector Multiplication on FPGAs, IEEE International Conference on Field-Programmable Technology (FPT2014), pp.290-291, 2014
  13. Hu, Guangxi; Xiang, Ping; Ding, Zhihao; Liu, Ran;Wang, Lingli; Tang, Ting-Ao, Analytical Models for Electric Potential, Threshold Voltage, and Subthreshold Swing of Junctionless Surrounding-Gate Transistors, IEEE Transactions on Electron Devices, Vol.61, No.3, pp.688-695, 2014
  14. Chaofan Yu,Lingli Wang, Chun Zhang, Yu Hu, Lei He, Fast Filter-Based Boolean Matchers, IEEE Embedded Systems Letters, Vol. 5, No. 4, pp. 65-68, December 2013
  15. Xitian Fan, Chenlu Wu, Wei Cao, Xuegong Zhou, Shengye Wang andLingli Wang, Implementation of High Performance Hardware Architecture of OpenSURF Algorithm on FPGA, IEEE International Conference on Field-Programmable Technology (FPT2013), pp.152-159, 2013
  16. Zheng Huang,Lingli Wang, Yakov Nasikovskiy and Alan Mishchenko, Fast Boolean Matching Based on NPN Classification, IEEE International Conference on Field-Programmable Technology (FPT2013), pp. 310-313, 2013
  17. Jialin Chen,Lingli Wangand Bin Wang, Quantum FPGA Architecture Design, IEEE International Conference on Field-Programmable Technology (FPT2013), pp. 354-357, 2013
  18. Shengye Wang, Chen Liang, Xuegong Zhou, Wei Cao, Chenlu Wu, Xitian Fan andLingli Wang, A Hardware Implementation of Bag of Words and Simhash for Image Recognition, IEEE International Conference on Field-Programmable Technology (FPT2013), pp.418-421, 2013
  19. Chen Liang, Chenlu Wu, Xuegong Zhou, Wei Cao, Shengye Wang andLingli Wang, An FPGA-Cluster-Accelerated Match Engine for Content-based Image Retrieval, IEEE International Conference on Field-Programmable Technology (FPT2013), pp.422-425, 2013
  20. Jialin Chen,Lingli Wang, Edoardo Charbon, and Bin Wang, Programmable Architecture for Quantum Computing, Physical Review A (88), 022311, 2013
  21. Ying Wang, Xuegong Zhou,Lingli Wang, Jian Yan, Wayne Luk, Chenglian Peng and Jiarong Tong, SPREAD: A Streaming-based Partially Reconfigurable Architecture and Programming Model, IEEE Transactions on Very Large Scale Integration Systems,Vol.21, No.12, pp. 2179-2192, 2013
  22. Guangxi Hu, Shuyan Hu, Ran Liu,Lingli Wang, Xing Zhou, Ting-Ao Tang, Quasi-Ballistic Transport Model for Graphene Field-Effect Transistor, IEEE Transactions on Electron Devices, Vol. 60, No. 7, p 2410-2414, 2013
  23. Zheng Huang,Lingli Wang, Yakov Nasikovskiy, Alan Mishchenko, Fast Boolean Matching for Small Practical Functions, Proc. International Workshop on Logic Synthesis (IWLS), pp.30-36, 2013
  24. Wenlong Yang,Lingli Wang, and Alan Mishchenko, Lazy Man’s Logic Synthesis, International Conference on Computer-Aided Design (ICCAD), pp.597-604, 2012
  25. W. Yang,L. Wang, and A. Mishchenko, "LMS: A new logic synthesis method based on pre-computed library", Proc. International Workshop on Logic Synthesis (IWLS), pp. 1-9, 2012
  26. Ying Wang, Jian Yan, Xuegong Zhou,Lingli Wang, Wayne Luk, Chenglian Peng, Jiarong Tong, A Partially Reconfigurable Architecture Supporting Hardware Threads(Best Paper Nomination),IEEE International Conference on Field-Programmable Technology (FPT2012), pp.269-276, 2012
  27. F. Gong, H. Yu,L. Wang,L. He, A Parallel and Incremental Extraction of Variational Capacitance with Stochastic Geometric Moments, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.20, No.9, pp.1729-1737, 2012
  28. T. Eguia, S. X.-D. Tan, R. Shen, D. Li, E. H. Pacheco, M. Tirumala, L. Wang, General parameterized thermal modeling for high-performance microprocessor design”, IEEE Transactions on Very Large Scale Integrated Systems, Vol.20, No.2, pp.211-224, 2012
  29. 陳志輝,章淳,王穎,王伶俐,一種FPGA抗輻射工藝映射方法研究,電子學報, Vol.39, No.11, pp.2507-2512, 2011
  30. Kanwen Wang, Jialin Chen, Wei Cao, Ying Wang,Lingli Wang, Jiarong Tong, A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design,IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 58, No. 7, pp.432-436, 2011
  31. Kejie Ma, Lingli Wang, Xuegong Zhou, Sheldon X.-D.Tan, Jiarong Tong, General Switch Box Modeling and Optimization for FPGA Routing Architectures, pp.320-323, International Conference on Field-Programmable Technology(FPT2010), 2010
  32. Chun Zhang, Lerong Cheng,Lingli Wang, Jiarong Tong, FPGA power and timing optimization: architecture, process, and CAD, 2010 International Conference on Computational Problem-Solving (ICCP), Invited Talk,pp.350 - 354, 2010
  33. Chun Zhang, Yu Hu,Lingli Wang, Lei He, and Jiarong Tong,Accelerating Boolean Matching Using Bloom Filter,IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E93-ANo.10pp.1775-1781, 2010/10
  34. C. Zhang, Y. Hu,L. Wang, J. Tong and L. He,Engineering a Scalable Boolean Matching Based on EDA SaaS 2.0, The International Conference on Computer-Aided Design (ICCAD), San Jose, CA., pp. 750-755, 2010
  35. C. Zhang, Y. Hu,L. Wang, J. Tong and L. He,Building A Faster Boolean Matcher Using Bloom Filter,Proceedings of 18ACM International Symposium on Field Programmable Gate Arrays 2010,pp.185-188, Feb. 2010
  36. HU Guang-Xi,WANG Lingli, LIU Ran, TANG Ting-Ao, Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors, Commun. Theor. Phys., Chinese Physical Society, pp. 763-767, Vol. 54, No. 4, 2010
  37. 龔愛慧,梁紹池,陳志輝,王伶俐,童家榕, CSPack:採用CSP圖匹配的新型裝箱算法,計算機輔助設計與圖形學學報, Vol.22, No.11, pp.1998-2003, 2010
  38. 汪鵬君,李輝,吳文晉,王伶俐,張小穎,戴靜,量子遺傳算法在多輸出Reed—Muller邏輯電路最佳極性搜尋中的套用,電子學報,Vol.38, No.5, pp.1058-1063, 2010
  39. Jia-Lin Chen, Edoardo Charbon, Lingli Wang, Wen-Qing Zhao, Quantum Gate Array Architecture Design Using Photons, International Conference on Quantum Foundation and Technology(ICQFT’09), 2009
  40. Guang-Xi Hu, Ran Liu, Ting-Ao Tang, andLing-Li Wang,Analytic Investigation on Threshold Voltage of Fully-depleted Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect-Transistors, Journal of the Korean Physical Society,Vol. 52, No. 6, pp.1909–1912, 2008
  41. 談珺,申秋實,王伶俐,童家榕, FPGA通用開關盒層次化建模與最佳化,電子與信息學報,第30卷,第5期, pp.1239-1242, 2008
  42. M. Yang,L. Wang,J.R. Tong, A.E.A. Almaini, Techniques for Dual Forms of Reed–Muller Expansion Conversion,Integration, the VLSI Journal,Vol. 41, No. 1, pp.113-122, 2008
  43. 胡云,王伶俐,唐璞山,童家榕,基於機率增益的電路劃分算法,電子與信息學報,Vol.29,No.11, pp.2762-2766, 2007
  44. Guang-Xi Hu, Ran Liu, Ting-Ao Tang, Shi-Jin Ding, andLing-Li Wang, Theory of Short-Channel Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect-Transistors, Japanese Journal of Applied Physics, Vol. 46, No. 4A, pp. 1437–1440,2007
  45. 胡云,王伶俐,唐璞山,童家榕,基於布通率的FPGA裝箱算法,計算機輔助設計與圖形學學報,Vol.19, No.1, pp.108-113, 2007
  46. L. Wang,and A. E. A. Almaini, Multilevel Logic Simplification Based on Containment Recursive Paradigm,IEE Proceedings Computers and Digital Techniques, Vol.150, No.4, 218-226, 2003
  47. L. Wangand A. E. A. Almaini, Exact Minimisation of Large Multiple Output FPRM Functions, IEE Proceedings Computers and Digital Techniques, Vol.149, No.5, 203-212, 2002
  48. L. Wangand A. E. A. Almaini, Optimisation of Reed-Muller PLA Implementations, IEE Proceedings Circuits, Devices and Systems, Vol.149, No.2, 119-128, 2002
  49. L. Wangand A. E. A. Almaini, Multilevel Logic Minimization Using Functional Don't Cares, 14th International Conference on VLSI Design, IEEE Computer Society, Bangalore, India, 417-424, 2001
  50. X. Wu, M. Pedram, andL. Wang, Multi-Code State Assignment for Low Power Sequential Circuit Design, IEE Proceedings Circuits, Devices and Systems, Vol.147, No.5, 271-275, 2000
  51. L. Wang, A. E. A. Almaini, Fast Conversion Algorithm for Very Large Boolean Functions, IEE Electronics Letters, Vol.36, No.16, 1370-1371, 2000
  52. 王伶俐, L, Song, G. Wu, Xiexiong, Chen,基於雙向電流型CMOS電路的譜綜合,電子科學學刊, Vol.22, No.2, 310-315, 2000
  53. L. Wang, A. E. A. Almaini, and A. Bystrov, Efficient Polarity Conversion for Large Boolean Functions, IEE Proceedings Computers and Digital Techniques, Vol.146, No.4, 197-204, 1999
  54. L. Wang,X. Chen, and A. E. A. Almaini, Algebraic Properties ofMultiple-Valued Modulo Systems and Their Applications to Current-Mode CMOS Circuits, IEE Proceedings Computers and Digital Techniques, Vol.145, No.5, 364-368, 1998
  55. L. Wang, X. Chen, and A. E. A. Almaini, Modulo Correlativity and its Application in a Multiple Valued Logic System, International J. Electronics, Vol.85, No.5, 561-570, 1998
  56. 王伶俐, Xiexiong Chen, and Xunwei Wu,模為合數時多值模代數的模減與模除運算,電子學報, Vol.26, No.5, 17-20, 1998
  57. 王伶俐, Xinmin Xu, Xiexiong Chen,基於模運算模為合數的多值邏輯函式的展開,電子科學學刊, Vol.20, No.1, 120-124, 1998
  58. 范雅俊,王伶俐,陳偕雄,基於多值模相關性的電流型CMOS電路設計,電路與系統學報,Vol.3,No.2, pp.43-49, 1998
  59. 王伶俐,陳偕雄,不完全確定序列機狀態化簡,電路與系統學報,Vol.1,No.3, pp.72-76, 1996

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