李清安：男，博士，武漢大學計算機學院副教授
基本介紹
- 中文名：李清安
- 學位/學歷：博士
- 職稱：副教授
- 性別：男
2014年2月畢業於香港城市大學（與武漢大學聯合培養），獲博士學位。 2013年12月畢業於武漢大學計算機軟體與理論專業，獲博士學位。 2008年6月畢業於武漢大學計算機學院，獲學士學位。研究領域包括編譯最佳化、嵌入式系統和軟體分析等。先後發表30餘篇論文在TC、TPDS、TVLSI、TCAD、TODEAS等IEEE/ACM Transactions國際權威期刊和DATE、LCTES、DAC、ISLPED、ASP-DAC、CASES、TrustCom等重要國際會議上。主持和參與多項國家和省部級科研項目。
- 發表論文
1. Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems, Keni Qiu, Qingan Li, Jingtong Hu, Weigong Zhang, Chun Jason Xue, accepted in IEEE Transactions on Computers (TC) (2015) (CCF A) Accepted.
2. Qingan Li, Yanxiang He, Jianhua Li, Liang Shi, Yiran Chen, Chun Jason Xue: Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache. IEEE Trans. Computers 64(8): 2169-2181 (2015) (CCF A)
3. Qingan Li, Jianhua Li, Liang Shi, Mengying Zhao, Chun Jason Xue, Yanxiang He: Compiler-Assisted STT-RAM-Based Hybrid Cache for Energy Efficient Embedded Systems. IEEE Trans. VLSI Syst. 22(8): 1829-1840 (2014) (CCF B)
4. Jianhua Li, Liang Shi, Qingan Li, Chun Jason Xue, Yinlong Xu: Thread Progress Aware Coherence Adaption for Hybrid Cache Coherence Protocols. IEEE Trans. Parallel Distrib. Syst. 25(10): 2697-2707 (2014) (CCF A)
5. Keni Qiu, Mengying Zhao, Qingan Li, Chenchen Fu, Chun Jason Xue: Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 33(3): 329-342 (2014) (CCF B)
6. Yazhi Huang, Liang Shi, Jianhua Li, Qingan Li, Chun Jason Xue: WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture. IEEE Trans. VLSI Syst. 22(1): 168-180 (2014) (CCF B)
7. Liang Shi, Jianhua Li, Qingan Li. Xue, C.J, Chengmo Yang, Xuehai Zhou, "A Unified Write Buffer Cache Management Scheme for Flash Memory," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.22, no.12, pp.2779,2792, Dec. 2014 (CCF B)
8. Jianhua Li, Liang Shi, Qingan Li, Chun Jason Xue, Yiran Chen, Yinlong Xu, Wei Wang: Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh. ACM Trans. Design Autom. Electr. Syst. 19(1): 5 (2013) (CCF B)
9. Wanyong Tian, Yingchao Zhao, Liang Shi, Qingan Li, Jianhua Li, Chun Jason Xue, Minming Li, Enhong Chen: Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory. IEEE Trans. VLSI Syst. 21(7): 1271-1284 (2013) (CCF B)
2. Qingan Li, Yanxiang He, Jianhua Li, Liang Shi, Yiran Chen, Chun Jason Xue: Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache. IEEE Trans. Computers 64(8): 2169-2181 (2015) (CCF A)
3. Qingan Li, Jianhua Li, Liang Shi, Mengying Zhao, Chun Jason Xue, Yanxiang He: Compiler-Assisted STT-RAM-Based Hybrid Cache for Energy Efficient Embedded Systems. IEEE Trans. VLSI Syst. 22(8): 1829-1840 (2014) (CCF B)
4. Jianhua Li, Liang Shi, Qingan Li, Chun Jason Xue, Yinlong Xu: Thread Progress Aware Coherence Adaption for Hybrid Cache Coherence Protocols. IEEE Trans. Parallel Distrib. Syst. 25(10): 2697-2707 (2014) (CCF A)
5. Keni Qiu, Mengying Zhao, Qingan Li, Chenchen Fu, Chun Jason Xue: Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 33(3): 329-342 (2014) (CCF B)
6. Yazhi Huang, Liang Shi, Jianhua Li, Qingan Li, Chun Jason Xue: WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture. IEEE Trans. VLSI Syst. 22(1): 168-180 (2014) (CCF B)
7. Liang Shi, Jianhua Li, Qingan Li. Xue, C.J, Chengmo Yang, Xuehai Zhou, "A Unified Write Buffer Cache Management Scheme for Flash Memory," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.22, no.12, pp.2779,2792, Dec. 2014 (CCF B)
8. Jianhua Li, Liang Shi, Qingan Li, Chun Jason Xue, Yiran Chen, Yinlong Xu, Wei Wang: Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh. ACM Trans. Design Autom. Electr. Syst. 19(1): 5 (2013) (CCF B)
9. Wanyong Tian, Yingchao Zhao, Liang Shi, Qingan Li, Jianhua Li, Chun Jason Xue, Minming Li, Enhong Chen: Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory. IEEE Trans. VLSI Syst. 21(7): 1271-1284 (2013) (CCF B)
