成元慶

成元慶

成元慶，男，畢業於中國科學院計算技術研究所，博士。現任職於北京航空航天大學微電子學院。

基本介紹

  • 中文名：成元慶
  • 畢業院校：中國科學院計算技術研究所
  • 學位/學歷：博士
  • 職業：教師
  • 專業方向：新型半導體器件的低功耗設計技術等
  • 任職院校：北京航空航天大學微電子學院
研究方向,主講課程,人物經歷,科研成果,

研究方向

  1. 基於新型半導體器件的低功耗設計技術
  2. 三維積體電路體系結構設計及設計自動化技術

主講課程

微機原理與接口技術

人物經歷

教育經歷
  1. 中國科學院計算技術研究所 博士學位 | 博士研究生畢業
  2. 哈爾濱工業大學 Master's Degree | 碩士研究生畢業
  3. 西安電子科技大學 Bachelor's Degree | 大學本科畢業
工作經歷
  1. 美國加州大學聖芭芭拉分校 | 訪問學者
  2. 北京航空航天大學 | 微電子學院
  3. 法國CNRS-LIRMM | 微電子 | 博士後
社會兼職
  1. 2017.3-至今PATMOS會議 TPC
  2. 2018.3-2022.3DATE TPC委員
  3. 2019.3-至今IEICE會員
  4. 2013.3-至今 IEEE會員
  5. 2012.3-至今ACM會員
  6. 2018.3-至今CCF體系結構專委委員
  7. 2016.3-至今CCF高級會員

科研成果

承擔過國家自然科學基金青年基金1項，北京市自然科學基金青年項目1項，北航“藍天新秀”專項基金1項。在研北京市自然科學基金面上項目1項，計算機體系結構國家重點實驗室開放課題1項，航天二院航天科學基金1項。
參與編纂英文學術專著1部，發表包括ICCAD, IEEE Trans. on CAD, IEEE Trans. on VLSI等在內40餘篇學術論文。榮獲2017年北京市科學技術二等獎1項。
科研項目
  1. 基於STT-MRAM的存儲計算架構設計研究
  2. 北京航空航天大學“藍天新秀”人才專項, 已結題
  3. 基於自旋轉移矩磁性存儲器的片上高速快取可靠性設計方法研究, 已結題
  4. 基於STT-MRAM的三維片上多核系統快取低功耗設計方法研究, 已結題
學術論文
  1. [c1] Yuanqing Cheng, Lei Zhang, Yinhe Han, Jun Liu and Xiaowei Li, "Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC", in Proceedings of IEEE Asian Test Symposium (ATS), New Delhi, India, Nov. 2011, pp. 181-186.
  2. [c2] Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vevet and Marc Belleville, "A novel method to mitigate TSV electromigration for 3D ICs", in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Natal, Brazil, Jul. 2013, pp. 121-126.
  3. [j1] Yuanqing Cheng, Lei Zhang, Yinhe Han, and Xiaowei Li, "TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design", Journal of Computer Science and Technology (JCST), vol. 28, no. 1, pp. 119-128, 2013.
  4. [j2] Yuanqing Cheng, Lei Zhang, Yinhe Han, and Xiaowei Li, "Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 21, no. 2, pp. 239-249, 2013.
  5. [c3] Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, and Arnaud Virazel, "Power Supply Noise-Aware Workload Assignments for Homogenous 3D MPSoCs with Thermal Consideration", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, Jan. 2014, pp.544-549.
  6. [c4] Xiaolong Zhang, Yuanqing Cheng*, Weisheng Zhao, Youguang Zhang and Aida Todri-Sanial, "Exploring Potentials of Perpendicular Magnetic Anisotropy STT-MRAM for Cache Design", in Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Guilin, China, Oct. 2014, pp. 893-895.
  7. [c5] Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng and Xiaowei Li, "HARS: A High-Performance Reliable Routing Scheme for 3D NoCs", in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, USA, Jul. 2014, pp. 392-397.
  8. [c6] Lun Yang, Yuanqing Cheng*, Ying Wang, Hao Yu, Weisheng Zhao and Aida Todri-Sanial, "A body-biasing of readout circuit for STT-RAM with improved thermal reliability", in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015, pp. 1530-1533.
  9. [c7] Xiaolong Zhang, Yuanqing Cheng*, Ying Wang, Weisheng Zhao and Aida Todri-Sanial, "Write back energy optimization for STT-RAM based cache using data pattern characterization", IEEE/ACM Design Automation Conference (DAC) WIP session, San Francisco, CA, USA, Jun. 2015.
  10. [c8] Bi Wu, Yuanqing Cheng*, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres and Weisheng Zhao, "An architecture-level cache simulation framework supporting advanced PMA STT-MRAM", in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Boston, MA, USA, Jul. 2015, pp. 7-12.
  11. [c9] Liuyang Zhang, Wang Kang, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein and Weisheng Zhao, "Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM", in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, Jul. 2015, pp. 461-466.
  12. [c10] Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li and Xiaowei Li, "A case of precision-tunable STT-RAM memory design for approximate neural network", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015, pp. 1534-1537.
  13. [j3] Yuanqing Cheng*, Aida Todri-Sanial, Jianlei Yang and Weisheng Zhao, "Alleviating Through Silicon Via Electromigration for Three-dimensional Integrated Circuits Taking Advantage of Self-healing Effect", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 11, pp. 3310-3322, 2016.
  14. [c11] Ping Chi, Shuangchen Li, Yuanqing Cheng, Yv Lu, S. H. Kang and Yuan Xie, "Architecture Design with STT-RAM: Opportunities and Challenges", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China, Jan. 2016, pp.109-114.
  15. [j4] Aida Todri-Sanial and Yuanqing Cheng, "A Study of 3-D Power Delivery Networks With Multiple Clock Domains", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 11, pp. 3218-3231, 2016.
  16. [c12] Linuo Xue, Yuanqing Cheng*, Jianlei Yang, Peiyuan Wang and Yuan Xie, "ODESY: A novel 3T-3MTJ cell design with Optimized area DEnsity, Scalability and latency", in Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), Austin, TX, USA, Nov. 2016, pp. 1-8.
  17. "Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM", IEEE Transactions on Reliability, vol. 65, no. 4, pp. 1755-1768, 2016.
  18. [j5] Bi Wu, Yuanqing Cheng*, Jianlei Yang, Aida Todri-Sanial and Weisheng Zhao,
  19. [c13] Liang Wu, Xiaoxiao Wang, Xiaoying Zhao, Yuanqing Cheng, Donglin Su, Aixin Chen, Qihang Shi and Mark Tehranipoor, "AES design improvement towards information safety", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 1706-1709.
  20. [c14] Liuyang Zhang, Aida Todri-Sanial, Wang Kang, Youguang Zhang, Lionel Torres, Yuanqing Cheng* and Weisheng Zhao, "Quantitative evaluation of reliability and performance for STT-MRAM", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 1150-1153.
  21. [c15] Liting Yu, Xiaoxiao Wang, Yuanqing Cheng, Xiaoying Zhao, Pengyuan Jiao, Aixin Chen, Donglin Su, LeRoy Winemberg, Mehdi Sadi and Mark Mohammad Tehranipoor, "An efficient all-digital IR-Drop Alarmer for DVFS-based SoC", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 221-224.
  22. [j6] Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen and Hai (Helen) Li, "Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach". IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 35, no. 3, pp. 380-393, 2016.
  23. [j7] Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng and Xiaowei Li, "PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM". IEEE Transactions on Very Large Scale Integrated Systems, vol. 24, no. 5, pp. 1613-1625, 2016.
  24. [c16] Liu Liu, Ping Chi, Shuangchen Li, Yuanqing Cheng and Yuan Xie, "Building energy-efficient multi-level cell STT-RAM caches with data compression", in Proceedings of Asian & South Pacific Design Automation Conference (ASP-DAC), Chiba/Tokyo, Japan, Jan. 2017, pp. 751-756.
  25. [j8] Lili Song, Ying Wang, Yinhe Han, Huawei Li, Yuanqing Cheng and Xiaowei Li, "STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator", IEEE Transactions on Very Large Scale Integrated Systems vol. 25, no. 4, pp. 1285-1296, 2017.
  26. [c17] Bi Wu, Yuanqing Cheng*, Pengcheng Dai, Jianlei Yang, Youguang Zhang，Dijun Liu, Ying Wang and Weisheng Zhao, "Thermosiphon: A Thermal Aware NUCA Architecture for Write Energy Reduction of the STT-MRAM based LLCs", in Proceedings of International Symopsium on Computer Aided Design (ICCAD), Irvine, CA, USA, Nov. 2017, pp. 474-481.
  27. [j9] Linuo Xue, Bi Wu, Beibei Zhang, Yuanqing Cheng*, Peiyuan Wang, Chando Park, Jimmy Kan, Seung H.Kang and Yuan Xie, "An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM based LLCs", IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), vol. 26, no. 3, pp. 484-495, 2018.
  28. [j10] Yinglin Zhao, Yuanqing Cheng*, Jianlei Yang, Weisheng Zhao and Aida Todri-Sanial, "Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint", to appear on Journal of Computer Science and Technology (JCST), Springer.
  29. [c18] Chen Liu, Yuanqing Cheng*, Ying Wang, Youguang Zhang and Weisheng Zhao, "NEAR: a Novel Energy Aware Replacement Policy for STT-MRAM LLCs", to appear on IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.
  30. [j11] Liuyang Zhang, Yuanqing Cheng, Wang Kang, Lionel Torres, Zhangyouguang, Aida Todri-Sanial and Weisheng Zhao, "Addressing the Thermal Issues of STT-MRAM from Compact Modeling to Design Techniques", to appear on IEEE Transactions on Nanotechnology, 2018.
  31. [c19] Bi Wu, Beibei Zhang, Yuanqing Cheng*, Ying Wang, Dijun Liu, Aida Todri-Sanial and Weisheng Zhao, "Chameleon: A Thermally Adaptive Error Correction Code Design for STT-MRAM LLCs", to appear on IEEE/ACM Design Automation Conference (DAC) WIP session, San Francisco, CA, USA, Jun. 2018.
  32. PAPERS
  33. [1] Chapter 4 of "High Performance Computing for Big Data: Methodologies & Applications", Chapman & Hall/CRC Press, Taylor and Francis Group, 2017.1, 320 pages.
  34. BOOK CHAPTERS

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