CMOS超大規模積體電路設計（第四版）（英文版）

圖書內容

本書是本經典教材，該版本反映了近年來積體電路設計領域面貌的迅速變化，突出了延時、功耗、互連和魯棒性等關鍵因素的影響。內容涵蓋了從系統級到電路級的CMOS VLSI設計方法，介紹了CMOS積體電路的基本原理，設計的基本問題，基本電路和子系統的設計，以及CMOS系統的設計實例（包括一系列當前設計方法和CMOS的特有問題，以及測試、可測性設計和調試等技術）。全書加強了對業界積累的許多寶貴設計經驗的介紹。

本書可作為高等院校電子科學與技術、微電子學與固體電子學、積體電路工程、計算機科學與技術、自動化、汽車電子以及精密儀器製造等專業的本科生和研究生在CMOS積體電路設計方面的教科書，並可作為從事積體電路設計領域研究和技術工作的工程技術人員和高等院校教師的常備參考書。

目錄

Chapter 1 Welcome to VLSI 1

1.1 A Brief History 1

1.2 Preview 6

1.3 MOS Transistors 6

1.4 CMOS Logic 9

1.4.1 The Inverter 9

1.4.2 The NAND Gate 9

1.4.3 CMOS Logic Gates 9

1.4.4 The NOR Gate 11

1.4.5 Compound Gates 11

1.4.6 Pass Transistors and Transmission Gates 12

1.4.7 Tristates 14

1.4.8 Multiplexers 15

1.4.9 Sequential Circuits 16

1.5 CMOS Fabrication and Layout 19

1.5.1 Inverter Cross-Section 19

1.5.2 Fabrication Process 20

1.5.3 Layout Design Rules 24

1.5.4 Gate Layouts 27

1.5.5 Stick Diagrams 28

1.6 Design Partitioning 29

1.6.1 Design Abstractions 30

1.6.2 Structured Design 31

1.6.3 Behavioral, Structural, and Physical Domains 31

1.7 Example: A Simple MIPS Microprocessor 33

1.7.1 MIPS Architecture 33

1.7.2 Multicycle MIPS Microarchitecture 34

1.8 Logic Design 38

1.8.1 Top-Level Interfaces 38

1.8.2 Block Diagrams 38

1.8.3 Hierarchy 40

1.8.4 Hardware Description Languages 40

1.9 Circuit Design 42

1.10 Physical Design 45

1.10.1 Floorplanning 45

1.10.2 Standard Cells 48

1.10.3 Pitch Matching 50

1.10.4 Slice Plans 50

1.10.5 Arrays 51

1.10.6 Area Estimation 51

1.11 Design Veri.cation 53

1.12 Fabrication, Packaging, and Testing 54

Summary and a Look Ahead 55

Exercises 57

Chapter 2 Devices 61

2.1 Introduction 61

2.2 Long-Channel I-V Characteristics 64

2.3 C-V Characteristics 68

2.3.1 Simple MOS Capacitance Models 68

2.3.2 Detailed MOS Gate Capacitance Model 70

2.3.3 Detailed MOS Diffusion Capacitance Model 72

2.4 Nonideal I-V Effects 74

2.4.1 Mobility Degradation and Velocity Saturation 75

2.4.2 Channel Length Modulation 78

2.4.3 Threshold Voltage Effects 79

2.4.4 Leakage 80

2.4.5 Temperature Dependence 85

2.4.6 Geometry Dependence 86

2.4.7 Summary 86

2.5 DC Transfer Characteristics 87

2.5.1 Static CMOS Inverter DC Characteristics 88

2.5.2 Beta Ratio Effects 90

2.5.3 Noise Margin 91

2.5.4 Pass Transistor DC Characteristics 92

2.6 Pitfalls and Fallacies 93

Summary 94

Exercises 95

Chapter 3 Speed 99

3.1 Introduction 99

3.1.1 De.nitions 99

3.1.2 Timing Optimization 100

3.2 Transient Response 101

3.3 RC Delay Model 104

3.3.1 Effective Resistance 104

3.3.2 Gate and Diffusion Capacitance 105

3.3.3 Equivalent RC Circuits 105

3.3.4 Transient Response 106

3.3.5 Elmore Delay 108

3.3.6 Layout Dependence of Capacitance 111

3.3.7 Determining Effective Resistance 112

3.4 Linear Delay Model 113

3.4.1 Logical Effort 114

3.4.2 Parasitic Delay 114

3.4.3 Delay in a Logic Gate 116

3.4.4 Drive 117

3.4.5 Extracting Logical Effort from Datasheets 117

3.4.6 Limitations to the Linear Delay Model 118

3.5 Logical Effort of Paths 121

3.5.1 Delay in Multistage Logic Networks 121

3.5.2 Choosing the Best Number of Stages 124

3.5.3 Example 126

3.5.4 Summary and Observations 127

3.5.5 Limitations of Logical Effort 129

3.5.6 Iterative Solutions for Sizing 129

3.6 Timing Analysis Delay Models 131

3.6.1 Slope-Based Linear Model 131

3.6.2 Nonlinear Delay Model 132

3.6.3 Current Source Model 132

3.7 Pitfalls and Fallacies 132

3.8 Historical Perspectives 133

Summary 134

Exercises 134

Chapter 4 Power 139

4.1 Introduction 139

4.1.1 De.nitions 140

4.1.2 Examples 140

4.1.3 Sources of Power Dissipation 142

4.2 Dynamic Power 143

4.2.1 Activity Factor 144

4.2.2 Capacitance 146

4.2.3 Voltage 148

4.2.4 Frequency 150

4.2.5 Short-Circuit Current 151

4.2.6 Resonant Circuits 151

4.3 Static Power 152

4.3.1 Static Power Sources 152

4.3.2 Power Gating 155

4.3.3 Multiple Threshold Voltages and Oxide Thicknesses 157

4.3.4 Variable Threshold Voltages 157

4.3.5 Input Vector Control 158

4.4 Energy-Delay Optimization 158

4.4.1 Minimum Energy 158

4.4.2 Minimum Energy-Delay Product 161

4.4.3 Minimum Energy Under a Delay Constraint 161

4.5 Low Power Architectures 162

4.5.1 Microarchitecture 162

4.5.2 Parallelism and Pipelining 162

4.5.3 Power Management Modes 163

4.6 Pitfalls and Fallacies 164

4.7 Historical Perspective 165

Summary 167

Exercises 167

Chapter 5 Wires 169

5.1 Introduction 169

5.1.1 Wire Geometry 169

5.1.2 Example: Intel Metal Stacks 170

5.2 Interconnect Modeling 171

5.2.1 Resistance 172

5.2.2 Capacitance 173

5.2.3 Inductance 176

5.2.4 Skin Effect 177

5.2.5 Temperature Dependence 178

5.3 Interconnect Impact 178

5.3.1 Delay 178

5.3.2 Energy 180

5.3.3 Crosstalk 180

5.3.4 Inductive Effects 182

5.3.5 An Aside on Effective Resistance and Elmore Delay 185

5.4 Interconnect Engineering 187

5.4.1 Width, Spacing, and Layer 187

5.4.2 Repeaters 188

5.4.3 Crosstalk Control 190

5.4.4 Low-Swing Signaling 192

5.4.5 Regenerators 194

5.5 Logical Effort with Wires 194

5.6 Pitfalls and Fallacies 195

Summary 196

Exercises 196

Chapter 6 Scaling, Reliability, and Variability 199

6.1 Introduction 199

6.2 Variability 199

6.2.1 Supply Voltage 200

6.2.2 Temperature 200

6.2.3 Process Variation 201

6.2.4 Design Corners 202

6.3 Reliability 204

6.3.1 Reliability Terminology 204

6.3.2 Oxide Wearout 205

6.3.3 Interconnect Wearout 207

6.3.4 Soft Errors 209

6.3.5 Overvoltage Failure 210

6.3.6 Latchup 211

6.4 Scaling 212

6.4.1 Transistor Scaling 213

6.4.2 Interconnect Scaling 215

6.4.3 International Technology Roadmap for Semiconductors 216

6.4.4 Impacts on Design 217

6.5 Statistical Analysis of Variability 221

6.5.1 Properties of Random Variables 221

6.5.2 Variation Sources 224

6.5.3 Variation Impacts 227

6.6 Variation-Tolerant Design 232

6.6.1 Adaptive Control 233

6.6.2 Fault Tolerance 233

6.7 Pitfalls and Fallacies 235

6.8 Historical Perspective 236

Summary 242

Exercises 242

Chapter 7 SPICE 245

7.1 Introduction 245

7.2 A SPICE Tutorial 246

7.2.1 Sources and Passive Components 246

7.2.2 Transistor DC Analysis 250

7.2.3 Inverter Transient Analysis 250

7.2.4 Subcircuits and Measurement 252

7.2.5 Optimization 254

7.2.6 Other HSPICE Commands 256

7.3 Device Models 256

7.3.1 Level 1 Models 257

7.3.2 Level 2 and 3 Models 258

7.3.3 BSIM Models 258

7.3.4 Diffusion Capacitance Models 258

7.3.5 Design Corners 260

7.4 Device Characterization 261

7.4.1 I-V Characteristics 261

7.4.2 Threshold Voltage 264

7.4.3 Gate Capacitance 266

7.4.4 Parasitic Capacitance 266

7.4.5 Effective Resistance 268

7.4.6 Comparison of Processes 269

7.4.7 Process and Environmental Sensitivity 271

7.5 Circuit Characterization 271

7.5.1 Path Simulations 271

7.5.2 DC Transfer Characteristics 273

7.5.3 Logical Effort 273

7.5.4 Power and Energy 276

7.5.5 Simulating Mismatches 277

7.5.6 Monte Carlo Simulation 277

7.6 Interconnect Simulation 277

7.7 Pitfalls and Fallacies 280

Summary 282

Exercises 282

Chapter 8 Gates 285

8.1 Introduction 285

8.2 Circuit Families 286

8.2.1 Static CMOS 287

8.2.2 Ratioed Circuits 292

8.2.3 Cascode Voltage Switch Logic 297

8.2.4 Dynamic Circuits 297

8.2.5 Pass-Transistor Circuits 307

8.3 Circuit Pitfalls 312

8.3.1 Threshold Drops 313

8.3.2 Ratio Failures 313

8.3.3 Leakage 314

8.3.4 Charge Sharing 314

8.3.5 Power Supply Noise 314

8.3.6 Hot Spots 315

8.3.7 Minority Carrier Injection 315

8.3.8 Back-Gate Coupling 316

8.3.9 Diffusion Input Noise Sensitivity 316