Axel Jantsch

人物信息

Axel Jantsch：男，電子科技大學教授。

教育背景

1982/10-1988/01，維也納科技大學，信息工程本科/碩士，導師：Grechenig教授

1988/01-1992/12，維也納科技大學，計算機科學博士，導師：Grünbacher教授

工作履歷

1993/04-1995/03，瑞典皇家理工學院，電子系統設計實驗室，博士後，合作導師：Hannu Tenhunen教授

1997/08-2002/02，瑞典皇家理工學院，信息與通信技術學院，電子系統系，副教授

2002/02-2014/10，瑞典皇家理工學院，信息與通信技術學院，電子系統系，正教授

2009/10-2014/10，瑞典皇家理工學院，信息與通信技術學院，電子系統系，系主任

2012/04-2016/04，復旦大學，無錫研究院，教授/千人計畫專家

2016/04-今，電子科技大學，微電子與固體電子學院，教授/千人計畫專家

學術兼職

2001－2005 2008-2013 DATE (Design Automation and Test in Europe) TPC Member

2009 NoCS (International Symposium on Networks on Chip) Co-Chair

榮譽獎勵

Axel Jantsch(3/3), Highway in TDM NoCs, International Symposium on Networks on Chip, 最佳論文獎, 2015. (Shaoteng Liu, Zhonghai Lu, andAxel Jantsch)

Axel Jantsch(3/3), A dynamically reconfigurable fpga-based content addressable memory for internet protocol characterization, the 10th International Conference on Field Programmable Logic and Applications, 最佳論文獎, 2000. (Johan Ditmar, Kjell Torkelsson, and Axel Jantsch)

研究領域

主要研究領域為多核/多處理器SoC設計，主要包括：

高能效多核異構片上多處理器系統（MPSoC）設計與實現：

研究如何在單一晶片中集成包含微處理器（MPU）、數位訊號處理器（DSP）、專用指令集處理器（ASIP）多種不同的處理器，研究系統架構及編程模型。

信息物理片上微系統（CPSoC）設計與實現：

研究片上感測器及讀出電路設計與片上網路技術相結合，研究完善的片上微環境感知方法，提出了基於片上微環境感知自適應片上微系統設計方法，研究如何實現以感知片上系統微環境為基礎的自適應（Self-Aware）片上微系統。

低功耗/高可靠容錯片上網路：

針對電壓持續降低導致的器件級物理效應，從關鍵電路/交換結構/網路體系等多個層面協同最佳化設計高可靠的容錯片上網路。

Axel jantshc教授是片上網路領域的開拓者之一。他和合作研究這於2000年就明確定義了片上網路（Network on Chip）的概念，並於2003年出版了世界上首本片上網路領域的學術專著。他所發表的論文他引次數已經超過7700次，最高單篇他引超過1300次。

學術成果

近3年發表的主要期刊論文：

1. Huang, L(#)(*)，Wang, J，Ebrahimi, M，Daneshtalab, M，Zhang, X，Li,G，Jantsch, A(*)，Non-Blocking Testing for Network-on-Chip，IEEE Transactionson Computers，2016，65（3）：679-692.

2. Fahimeh Jafari#*, Zhonghai Lu, andAxel Jantsch*. Least upper delay bound for VBR flows in networks-on-chip with virtual channels.ACM Transactions on. Design Automation of Electronic System, 2015, 20(3): 35:1-35:33.

3. Nikil Dutt#*,Axel Jantsch, and Santanu Sarma*. Towards smart embedded systems: A self-aware system-on-chip perspective.ACM Transactions on Embedded Computing Systems, 2016, 15(2):22.

4. Xiaowen Chen#*, Zhonghai Lu,Axel Jantsch, Shuming Chen, Yang Guo, Shenggang Chen, and HuChen*. Performance analysis of homogeneous on-chip large-scale parallel computing architectures for data-parallel applications.Journal of Electrical and Computer Engineering, 2015, 22, 2015.

5. Shaoteng Liu#*,Axel Jantsch, and Zhonghai Lu*. MultiCS: Circuit switched NoC with multiple sub-networks and sub-channels.Journal of Systems Architecture, 2015, 61(9):423-434.

6. AwetYemane Weldezion#*, Matt Grange,Axel Jantsch, Hannu Tenhunen, and Dinesh Pamunuwa*. Zero-load predictive model for performance analysis in deflection routing NoCs.Journal of Microprocessors and Microsystems, 2015, 39(8):634-647.

7. J.-S. Preden#*, K.Tammemäe,A.Jantsch, M.Leier, A.Riid, and E.Calis*. The benefits of self-awareness and attention in fog and mist computing.IEEE Computer, 2015,2015(7):37-45.

8. Andreas Steininger#*, Horst Zimmermann,Axel Jantsch, Michael Hofbauer, Ulrich Schmid, Kurt Schweiger, and VaradanSavulimedu Veeravalli*. Building reliable systems-on-chip in nanoscale technologies.Elektrotechnik & Informationstechnik, 2015, 132(6):301-306.

9. Yuang Zhang#*, LiLi, Zhonghai Lu,Axel Jantsch, Minglun Gao, Hongbing Pan, and Feng Han*. A survey of memory architecture for 3d chip multi-processors.Microprocessors and Microsystems, 2014, 38(5):415-430.

10. Xiaowen Chen#*, Zhonghai Lu,Axel Jantsch, Shuming Chen, Yang Guo, and Hengzhu Liu*. Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core nocs.IEICE Electronics Express, 2014, 11(18):20140542--20140542.

近3年發表的主要會議論文：

1.Axel Jantsch#* and Kalle Tammemäe. A framework of awareness for artificial subjects.2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES '14, New York, USA, 2014.10.12-2014.10.17.

2. Nima TaheriNejad#*, Sai ManojP. D., andAxel Jantsch*. Memristors' potential for multi-bit storage and pattern learning.the 9th European Modelling Symposium on Mathematical Modelling and Computer Simulation, Madrid, Spain, 2015.10.6-2015.10.8.

3. Junshi Wang#, Masoumeh Ebrahimi, Letian Huang*,Axel Jantsch*, and Guangjun Li, Design of Fault-Tolerant and Reliable Networks-on-Chip, 2015 IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, 2015.07.08-2012.07.10

4. Xiaofan Zhang#, Masoumeh Ebrahimi, Letian Huang*, Guangjun Li, andAxel Jantsch*. A network-level solution for fault detection, masking, and tolerance in NoCs.23rd IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing, (PDP), Turku, Finland, 2015.3.4-2015.3.6.

5. Shaoteng Liu#*, Zhonghai Lu, andAxel Jantsch*. Highway in TDM NoCs.the International Symposium on Networks on Chip, Vancouver, Canada, 2015.9.28-2015.9.30.(Best Paper Award).

6. Amirmohammad Rahmani#*, Hannu Tenhunen, Pasi Liljeberg, AwetYemane Weldezion, Srinivasa Kanduru, Juha Plosila, Mohammadhashem Haghbayan, andAxel Jantsch*. Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach.the International Symposium on Low Power Electronics and Design, 2015.07.22-2015.07-24.

7. Masoumeh Ebrahimi#*, Junshi Wang, Letian Huang, Masoud Daneshtalab, andAxel Jantsch*. Rescuing healthy cores against disabled routers.the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), Amsterdam, Netherlands, 2014.10.1-2014.10.3

8. Nikil Dutt#*,Axel Jantsch, and Santanu Sarma*. Self-aware cyber-physical systems-on-chip.the International Conference for Computer Aided Design, Austin, Texas, USA, 2015.11.2-2015.11.6.

9. Anil Kanduri#*, Mohammad-Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg,Axel Jantsch, and Hannu Tenhunen*. Dark silicon aware runtime mapping for many-core systems: A patterning approach.the International Conference on Computer Design (ICCD), New York City, USA, 2015.10.3-2015.10.5.

10. Mohammad-Hashem Haghbayan#*, Anil Kanduri, Amir-Mohammad Rahmani, Pasi Liljeberg,Axel Jantsch, and Hannu Tenhunen*. MapPro: Proactive runtime mapping for dynamic workloads by quantifying ripple effect of applications on networks-on-chip.the International Symposium on Networks on Chip, Vancouver, Canada, 2015.9.28-2015.9.30.