[1] (A1 層次) Junkai Huang, Wanling Deng, Xueren Zheng, et al. A compact model for undoped symmetric double-gate polysilicon thin film transistors. IEEE Trans. Electron Devices,2010, 57(10): 2607-2615. (JCR-SCI 分區表2 區 Top, SCI 光碟版檢索號WOS:000283346500032; EI 光碟版檢索號:20103913262478)
[2] (A1 層次) Wanling Deng, Junkai Huang. A Physics-based approximation for the polysilicon thin-film transistors surface potential. IEEE Electron Device Letters, 2011,32(5):647-649. ( JCR-SCI 分區表2 區 Top,SCI 光碟版檢索號WOS:000289908500023;EI 光碟版檢索號:20111813955622)
[3] (A1 層次) Wanling Deng, Junkai Huang, Xiyue Li. Surface-Potential-Based Drain Current Model of Polysilicon TFTs With Gaussian and Exponential DOS Distribution. IEEE Trans. Electron Devices, 2012, 59(1): 94-100. ( JCR-SCI 分區表2 區 Top, SCI 光碟版檢索號WOS:000298756100014;EI 光碟版檢索號:20120214670361 )
[4] (A3 層次) Weiying Huang, Chenyuan Zhao, Wanling Deng, Junkai Huang(通訊作者). A new low-voltage CMOS voltage reference. Second International Conference on Electric Information and Control Engineering (ICEICE 2012). Lushan: IEEE Press, 2012. (EI 光碟版檢索)
[5] (A3 層次) Xiyue Li, Wanling Deng, Junkai Huang (通信作者) .Determination of the trap states distribution in Poly-Si films using the OEMS modulation. The 9th IEEE International Conference on ASIC (ASICON 2011). Xiamen: IEEE Press, 2011: 726-729. (EI 光碟版檢索)
[6] (A3 層次) Chenyuan Zhao, Junkai Huang (通信作者). A new high performance bandgap reference. The International Conference on Electronics, Communications and Control (ICECC2011). Ningbo: IEEE Press, 2011: 6067602. (EI 光碟版檢索號:20114714545114)
[7] (A3 層次) Junkai Huang, Xiaozhou Jiang, Wanling Deng. Characterization of trap states distribution in poly-Si TFTs using OEMS. Proceedings of the international symposium on photonics and optoelectronics (SOPO 2010). Chengdu: IEEE Press, 2010: 5504394. (EI 光碟版檢索號:20103013104291)
[8] (A3 層次) Junkai Huang, Liang Yang. MINO MRT-MRC Systems with Rate Adaptive Modulation. Proceedings of the International Conference on Networks Security, Wireless Communications and Trusted Computing (NSWCTC 2009). Wuhan: IEEE Press, 2009 :12-16(EI 光碟版檢索號:20093012206571)
[9] (A3 層次) Huang Junkai, Zheng Guandong. The Digital Hardware Design of the Passive Electron Tag Based on theProtocol of ISO/IEC 14443-A. The 7th International Conference on ASIC (ASICON2007). Guilin: IEEE Press, 2007:970-973. (EI 光碟版檢索號:20083211440804)
[10] (A3層次) Li Xiyue, Deng Wanling, Huang Junkai (通信作者). A physical surface-potential-based drain current model for polysilicon thin-film transistors, Journal of Semiconductors(半導體學報), 2012,33(3):034005. (EI光碟版檢索號:20121214886359)