郭建平(中山大學電子與信息工程學院副教授)

郭建平，男，博士，中山大學電子與信息工程學院副教授。

基本介紹

  • 中文名：郭建平
  • 畢業院校：香港中文大學
  • 學位/學歷：博士
  • 專業方向：模擬與數模混合積體電路、電源管理積體電路、雷射雷達晶片等
  • 任職院校：中山大學
研究方向,人物經歷,學術兼職,教育經歷,授課課程,學術成果,科研項目,科研成果,

研究方向

模擬與數模混合積體電路、電源管理積體電路、雷射雷達晶片、物聯網晶片等

人物經歷

學術兼職

International Conference on Integrated Circuits, Technologies and Applications (ICTA), TPC Member，2018−今
IEEE固態電路學會廣州分會（IEEE SSCS Guangzhou Chapter），副主席，2018−今
中山大學廣東省積體電路工程技術研究中心，副主任，2016−今
IEEE高級會員（Senior Member），2016−今

教育經歷

2007.08−2011.06，香港中文大學電子工程系，博士研究生（導師：Prof. Ka Nang Leung 梁加能教授）
2003.08−2006.04，西安電子科技大學電子工程學院，碩士研究生（導師：來新泉教授）
1999.08−2003.07，西安電子科技大學電子工程學院，本科

授課課程

專業及行業認知（大二）；模擬電子線路及實驗（大二）；模擬積體電路設計（大三）；模擬積體電路版圖設計實驗（大三）；高級模擬積體電路設計（研究生）

學術成果

科研項目

2019−2022，亞納秒全集成低壓差線性穩壓器關鍵技術研究，國家自然科學基金面上項目，項目負責人
2018-2020，基帶射頻一體化晶片關鍵技術研究及設計實現，企業橫向委託項目，項目負責人
2018−2020，套用於物聯網無源感知設備的低功耗高PSR全集成LDO穩壓器研究，國家自然科學基金青年基金，聯合申請（第一參與人；項目負責人：廣州大學曾衍翰副教授）
2017−2018，低功耗高集成度套用處理器SoC中的數字輔助控制電源管理方案研究，中山大學青年教師重點培育項目，項目負責人
2016−2019，面向下一代移動通信的GaN基射頻器件關鍵技術及系統套用，國家重點研發計畫，課題骨幹，中山大學項目負責人（與蘇州能訊高能半導體有限公司合作）
2016−2019，攜帶型北斗多模導航SoC中的高效率、高集成、高性能電源管理積體電路，廣州市珠江科技新星專項，項目負責人
2015−2018，民用高性能低成本北斗導航SoC晶片若干關鍵技術研究，廣東省自然科學基金面上項目，項目負責人
2014−2015，北斗多模衛星導航晶片關鍵電路IP核的研究與設計，廣東順德中山大學-卡內基梅隆大學國際聯合研究院先導項目，第一參與人（項目負責人：陳弟虎教授）
2013−2015，低功耗高性能能量自激型電源管理積體電路，國家自然科學基金青年基金，項目負責人
2012−2014，北斗/GPS多模衛星導航高性能晶片開發及產業化，廣東省戰略新興產業關鍵技術產業化專項，與廣州潤芯合作申請，中大第一參與人（中大負責人：陳弟虎教授）
2012−2013，中山大學“百人計畫”引進人才科研啟動經費，項目負責人

科研成果

截至2019年6月，授權中國發明專利12項，並在IC設計領域主流國際期刊與國際會議發表50多篇相關學術論文，SCI檢索24篇，其中13篇為IEEE期刊論文，包括3篇IC設計頂級期刊IEEE Journal of Solid-State Circuits （JSSC）論文、5篇功率電子頂級期刊IEEE Transactions on Power Electronics （TPEL）論文、及2篇電路與系統頂級期刊IEEE Transactions on Circuits and Systems I: Regular Papers（TCAS-I）論文。代表性科研論文如下：
  1. C. H. Hung, Y. Q. Zheng,J. Guoand K. N. Leung, “Bandwidth and Slew Rate Enhanced OTA with Sustainable Dynamic Bias,”IEEE Transactions on Circuits and Systems II: Express Brief(TCAS-II), accepted for publication.
  2. G. Li, H. Qian,J. Guo*, B. Mo, Y. Lu, and D. Chen, “Dual Active-Feedback Frequency Compensation for Output-Capacitorless LDO with Transient and Stability Enhancement in 65-nm CMOS,”IEEE Transactions onPower Electronics(TPEL), accepted for publication.
  3. Q.Cheng, W. Li, X. Tang, andJ. Guo*, “Design and Analysis of Three-Stage Amplifier for Driving pF-to-nF Capacitive Load Based on Local Q-Factor Control and Cascode Miller Compensation Techniques,”Electronics, 2019, 8(5), 572, pp. 1−18. (SCI, IF: 2.110).
  4. S. Bu, K. N. Leung, Y. Lu,J. Guo, and Y. Zheng, “A Fully Integrated Low-Dropout Regulator with Differentiator-Based Active Zero Compensation,”IEEE Transactions on Circuits and Systems I: Regular Papers(TCAS-I), Vol. 65, No. 10, pp. 3578−3591, Oct. 2018. (SCI, IF: 2.407).
  5. Z. Wang, B. Chen, L. Zhu, Y. Zheng,J. Guo*, D. Chen, M. Ho, and K. N. Leung, “A 3.3-MHz fast-response load-dependent-on/off-time buck-boost DC-DC converter with low-noise hybrid full-wave current sensor,”Microelectronics Journal, Vol. 74, No. 4, pp. 1−12, Apr. 2018. (SCI, IF: 1.163)
  6. S. Bu,J. Guo, and K. N. Leung*, “A 200-ps-Response-Time Output-Capacitorless Low-Dropout Regulator with Unity-Gain Bandwidth >100 MHz in 130-nm CMOS,”IEEE Transactions onPower Electronics(TPEL), Vol. 33, No. 4, pp. 3232−3246, Apr. 2018. (SCI, IF: 7.151)
  7. Y. Zheng, M. Ho,J. Guo*, and K. N. Leung, “A Single-Inductor Multiple-Output Auto-Buck-Boost DC-DC Converter with Tail-Current Control,”IEEE Transactions onPower Electronics(TPEL), Vol. 31, No. 11, pp. 7857−7875, Nov. 2016. (SCI, IF: 6.008)
  8. M. Ho,J. Guo, K. H. Mak, W. L. Goh, S. Bu, Y. Zheng, X. Tang, and K. N. Leung*, “A CMOS Low-Dropout Regulator with Dominant-Pole Substitution,”IEEE Transactions onPower Electronics(TPEL), Vol. 31, No. 9, pp. 6362−6371, Sep. 2016. (SCI, IF: 6.008)
  9. M. Ho,J. Guo, T. W. Mui, K. H. Mak, W. L. Goh, H. C. Poon, S. Bu, M. W. Lau, and K. N. Leung*, “A Two-Stage Large-Capacitive-Load Amplifier with Multiple Cross-Coupled Small-Gain Stages,”IEEE Transactions on VLSI Systems(TVLSI), Vol. 24, No. 7, pp. 2580−2592, Jul. 2016. (SCI, IF: 1.245)
  10. Y. Zheng, M. Ho,J. Guo, K-L Mak, and K. N. Leung*, “A Single-Inductor Multiple-Output Auto-Buck-Boost DC-DC Converter with Auto Phase Allocation,”IEEE Transactions onPower Electronics(TPEL), Vol. 31, No. 3, pp. 2296−2313, Mar. 2016. (SCI, IF: 6.008, Top accessed TPEL paper in Nov. 2015)
  11. J. Guo*, M. Ho, K. N. Leung, and G. Li, “Digitally-assisted constant-on-time dynamic-biasing technique for bandwidth and slew-rate enhancement in ultra-low-power low-dropout regulator,”International Journal of Circuit Theory and Applications(IJCTA), Vol. 44, No. 2, pp. 504−513, Feb. 2016. DOI: 10.1002/cta.2091. (SCI, IF: 1.254)
  12. K. H. Mak, M. W. Lau,J. Guo, T. W. Mui, M. Ho, W. L. Goh, and K. N. Leung*, “A 0.7-V 24-µA Hybrid OTA Driving 15-nF Capacitive Load with 1.46-MHz GBW,”IEEEJournal of Solid-State Circuits(JSSC), Vol. 50, No. 11, pp. 2750−2757, Nov. 2015. (SCI, IF: 3.009, Top 1 journal in IC design, Top accessed JSSC paper in Oct. and Nov. 2015)
  13. M. Huang, D. Chen,J.Guo*, H. Ye, K. Xu, X. Liang, and Y. Lu, “A CMOS Delta Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration,”IEEE Transactions on Circuits and Systems I: Regular Papers(TCAS-I), Vol. 62, No. 7, pp. 1716−1725, Jul. 2015. (SCI, IF: 2.403)
  14. M. Huang, D. Chen, Z. Wang,J.Guo*, E. H. Dagher, B. Xu, K. Xu, H. Ye, W. Zheng, Z. Liang, X. Liang, and W. K. Masenten, “A power-area-efficient, 3-band, 2-RX MIMO, TD-LTE receiver with direct-coupled ADC,”International Journal of Circuit Theory and Applications(IJCTA), pp. 806−821, Jun. 2015. (SCI, IF: 1.254)
  15. J. Guo*, M. Ho, K. Y. Kwong, and K. N. Leung, “Power-Area-Efficient Transient-Improved Capacitor-Free FVF-LDO With Digital Detecting Technique,”IET Electronics Letters(EL), Vol. 51, No. 1, pp. 94–96, Jan. 2015. (SCI, IF: 0.930, Top accessed EL paper in Jan., Mar., Apr., and Jun., 2015)
  16. M. Huang, D. Chen,J.Guo*, K. Xu, H. Ye, X. Liang, E. H. Dagher, B. Xu, and W. K. Masenten, “A Tri-Band, 2-RX MIMO, 1-TX TD-LTE CMOS Transceiver,”Microelectronics Journal, Vol. 46, No. 1, pp. 59−66, Jan. 2015. (SCI, IF: 0.836)
  17. T. W. Mui, M. Ho, K. H. Mak,J. Guo, H. Chen, and K. N. Leung*, “An Area-Efficient 96.5%-Peak-Efficiency Cross-Coupled Voltage Doubler With Minimum Supply of 0.8V,”IEEE Transactions on Circuits and Systems II: Express Brief(TCAS-II), Vol. 61, No. 9, pp. 656−660, Sep. 2014. (SCI, IF: 1.234)
  18. J. Guoand K. N. Leung*, “A CMOS Voltage Regulator for Passive RFID Tag ICs,”International Journal of Circuit Theory and Applications(IJCTA), Vol. 40, No. 4, pp. 329−340, Apr. 2012. (SCI, IF: 1.254)
  19. J. Guoand K. N. Leung*, “A 6-µW Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology,”IEEE Journal of Solid-State Circuits(JSSC), Vol. 45, No. 9, pp. 1896−1905, Sep. 2010. (SCI, IF: 3.009;Top 1journal in IC design;Most accessedJSSC paper in Sep. 2010, ranked 7th and 10th of the top 10 accessed JSSC paper in Oct. 2010 and Nov. 2010, respectively; Ranked 14th and 100th of the top 100 downloaded documents in Sep. 2010 and Nov. 2010, respectively, in IEEE Xplore)
  20. C. F. Chan, K. P. Pun*, K. N. Leung,J. Guo, L. L. K. Leung, and C. S. Choy, “Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders,”IEEE Journal of Solid-State Circuits(JSSC), Vol. 45, No. 3, pp. 587−599, Mar. 2010. (SCI, IF: 3.009;Top 1journal in IC design)
  21. J. Guo*, Y. Cao, and X. Lai, “An Inner ESR-Fungible Compensation Technique for CMOS Low Dropout Regulator,”Analog Integrated Circuits and Signal Processing(AICSP), Vol. 61, No. 3, pp. 265−270, Dec. 2009. (SCI, IF: 0.468)
  22. X. Lai,J. Guo*, Z. Sun, and J. Xie, “A 3-A CMOS Low Dropout Regulator with Adaptive Miller Compensation,”Analog Integrated Circuits and Signal Processing(AICSP), Vol. 49, No. 1, pp. 5−10, Oct. 2006. (SCI, IF: 0.468)
  23. J. Guoand K. N. Leung, “A 25mA CMOS LDO with −85dB PSRR at 2.5MHz,”IEEE Asian Solid-State Circuits Conference(A-SSCC), Singapore, pp. 381−384, Nov. 2013.
  24. J. Guoand K. N. Leung, “High PSRR LDO with Embedded Ripple Feed-Forward Path,”IEEE International Solid-State Circuits Conference(ISSCC), San Francisco, California, USA, Student Research Preview, Feb. 20, 2011. (Top 1conference in IC design, also known as "the Chip Olympics"，Student Travel Grant Award).

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