《超高頻多速開關電容電路設計(影印版)》是一本專業性很強的書，《超高頻多速開關電容電路設計(影印版)》以具體實例為依託，詳細闡述了作者所設計的一款性能優越、用途廣泛的高頻開關電容電路，並對該電路設計中所涉及到的模擬CMOS積體電路設計的很多重要問題進行講解。其實這些問題並不僅僅出現於《超高頻多速開關電容電路設計(影印版)》所介紹的這種電路類型，而是在模擬積體電路設計中經常會遇到的一些問題，所以該書的參考價值可以擴展到更大的領域。更難能可貴的是作者所設計的這款電路的優越性能得到了實際晶片測試的驗證，亦即增加了《超高頻多速開關電容電路設計(影印版)》的權威性。
基本介紹
- 書名：《超高頻多速開關電容電路設計》
- 出版社：科學出版社
- 頁數：260頁
- 開本：16
- 定價：35.00
- 作者：潘森 等
- 出版日期：2007年3月29日
- 語種：英語
- ISBN：7030182499, 9787030182494
- 品牌：科學出版社
內容簡介,圖書目錄,
內容簡介
《超高頻多速開關電容電路設計(影印版)》所論述的高頻開關電容電路屬於相關領域的研究熱點，是積體電路設計中不可迴避的前沿問題。此外，書中提出的設計方法具有很強的啟發性和指導性。相關的著作很少見，相信該書具有很高的權威性。
圖書目錄
Preface
Acknowledgment
List of Abbreviations
List of Figures
List of Tables
1 INTRODUCTION
1. High-Frequency Integrated Analog Filtering
2. Multirate Switched-Capacitor Circuit Techniques
3. Sampled-Data Interpolation Techniques
4. Research Goals and Design Challenges
2 IMPROVED MULTIRATE POLYPHASE-BASED INTERPOLATION STRUCTURES
1. Introduction
2. Conventional and Improved Analog Interpolation
3. Polyphase Structures for Optimum-class Improved Analog Interpolation
4. Multirate ADB Polyphase Structures
4.1 Canonic and Non-Canonic ADB Realizations
4.2 SC Circuit Architectures
5. Low-Sensitivity Multirate IIR Structures
5.1 Mixed Cascade/Parallel Form
5.2 Extra-Ripple IIR Form
6. Summary
3 PRACTICAL MULTIRATE SC CIRCUIT DESIGN CONSIDERATIONS
1. Introduction
2. Power Consumption Analysis
3. Capacitor-Ratio Sensitivity Analysis
3.1 FIR Structure
3.2 IIR Structure
4. Finite Gain & Bandwidth Effects
5. Input-Referred Offset Effects
6. Phase Timing-Mismatch Effects
6.1 Periodic Fixed Timing-Skew Effect
6.2 Random Timing-Jitter Effects
7. Noise Analysis
8. Summary
4 GAIN- AND OFFSET- COMPENSATION FOR MULTIRATE SC CIRCUITS
1. Introduction
2. Autozeroing and Correlated-Double Sampling Techniques
3. AZ and CDS SC Delay Blocks with Mismatch-Free Property
3.1 SC Delay Block Architectures
3.2 Gain and Offset Errors - Expressions and Simulation Verification
3.3 Multi-Unit Delay Implementations
4. AZ and CDS SC Accumulators
4.1 SC Accumulator Architectures
4.2 Gain and Offset Errors - Expressions and Simulation Verification
5. Design Examples
6. Speed and Power Considerations
7. Summary
5 DESIGN OF A 108 MHz MULTISTAGE SC VIDEO INTERPOLATING FILTER
1. Introduction
2. Optimum Architecture Design
2.1 Multistage Polyphase Structure with Half-Band Filtering..
2.2 Spread-Reduction Scheme
2.3 Coefficient-Sharing Techniques
3. Circuit Design
3.1 lst-Stage
3.2 2nd- and 3rd-Stage
3.3 Digital Clock Phase Generation
4. Circuit Layout
5. Simulation Results
5.1 BehavioraI Simulations
5.2 Circuit-Level Simulations
6. Summary
6 DESIGN OF A 320 MHZ FREQUENCY-TRANSLATED SC BANDPASS INTERPOLATING FILTER
1. Introduction
2. Prototype System-Level Design
2.1 Multi-notch FIR Transfer Function
2.2 Time-Interleaved Serial ADB Polyphase Structure with
A utozeroing
3. Prototype Circuit-Level Design
3.1 Autozeroing ADB and Accumulator
3.2 High-Speed Multiplexer
3.3 Overall SC Circuit Architecture
3.4 Telescopic opamp with Wide-Swing Biasing
3.5 nMOS Switches 136
3.6 Noise Calculation
3.7 I/0 Circuitry
3.8 Low Timing-Skew Clock Generation
4. Layout Considerations
4.1 Device and Path Matching
4.2 Substrate and Supply Noise Decoupling
4.3 Shielding
4.4 Floor Plan
5. Simulation Results
5.1 Opamp Simulations
5.2 Filter Behavioral Simulations
5.3 Filter Transistor-Level and Post-Layout Simulations
6. Summary
7 EXPERIMENTAL RESULTS
1. Introduction
2. PCB Design
2.1 Floor Plan
2.2 Power Supplies and Decoupling
2.3 Biasing Currents
2.4 Input and Output Network
3. Measurement Setup and Results
3.1 Frequency Response
3.2 Time-Domain Signal Waveforms
3.3 One-Tone Signal Spectrum
3.4 Two-Tone Intermodulation Distortion
3.5 THD and IM3 vs. Input Signal Level
3.6 Noise Performance
3.7 CMRR and PSRR
4. Summary
8 CONCLUSIONS
APPENDIX 1 TIMING-MISMATCH ERRORS WITH NONUNIFORMLY HOLDING EFFECTS
1. Spectrum Expressions for IU-ON(SH) and IN-CON(SH)
1.1 IU-ON(SH)
1.2 IN-CON(SH)
2. Closed Form SINAD Expression for IU-ON(SH) and IN-CON(SH)
2.1 IU-ON(SH)
2.2 IN-CON(SH)
3. Closed Form SFDR Expression for IN-CON(SH) systems
4. Spectrum Correlation of IN-OU(IS) and IU-ON(SH)
APPENDIX 2 NOISE ANALYSIS FOR SC ADB DELAY LINE AND POLYPHASE SUBFILTERS
1. Output Noise of ADB Delay Line
2. Output Noise of Polyphase Subfilters
2.1 Using TSI Input Coefficient SC Branches
2.2 Using OFR Input Coefficient SC Branches
APPENDIX 3 GAIN, PHASE AND OFFSET ERRORS FOR GOC MF SC DELAY CIRCUIT I AND J
1. GOC MF SC Delay Circuit I
2. GOC MF SC Delay Circuit J
Acknowledgment
List of Abbreviations
List of Figures
List of Tables
1 INTRODUCTION
1. High-Frequency Integrated Analog Filtering
2. Multirate Switched-Capacitor Circuit Techniques
3. Sampled-Data Interpolation Techniques
4. Research Goals and Design Challenges
2 IMPROVED MULTIRATE POLYPHASE-BASED INTERPOLATION STRUCTURES
1. Introduction
2. Conventional and Improved Analog Interpolation
3. Polyphase Structures for Optimum-class Improved Analog Interpolation
4. Multirate ADB Polyphase Structures
4.1 Canonic and Non-Canonic ADB Realizations
4.2 SC Circuit Architectures
5. Low-Sensitivity Multirate IIR Structures
5.1 Mixed Cascade/Parallel Form
5.2 Extra-Ripple IIR Form
6. Summary
3 PRACTICAL MULTIRATE SC CIRCUIT DESIGN CONSIDERATIONS
1. Introduction
2. Power Consumption Analysis
3. Capacitor-Ratio Sensitivity Analysis
3.1 FIR Structure
3.2 IIR Structure
4. Finite Gain & Bandwidth Effects
5. Input-Referred Offset Effects
6. Phase Timing-Mismatch Effects
6.1 Periodic Fixed Timing-Skew Effect
6.2 Random Timing-Jitter Effects
7. Noise Analysis
8. Summary
4 GAIN- AND OFFSET- COMPENSATION FOR MULTIRATE SC CIRCUITS
1. Introduction
2. Autozeroing and Correlated-Double Sampling Techniques
3. AZ and CDS SC Delay Blocks with Mismatch-Free Property
3.1 SC Delay Block Architectures
3.2 Gain and Offset Errors - Expressions and Simulation Verification
3.3 Multi-Unit Delay Implementations
4. AZ and CDS SC Accumulators
4.1 SC Accumulator Architectures
4.2 Gain and Offset Errors - Expressions and Simulation Verification
5. Design Examples
6. Speed and Power Considerations
7. Summary
5 DESIGN OF A 108 MHz MULTISTAGE SC VIDEO INTERPOLATING FILTER
1. Introduction
2. Optimum Architecture Design
2.1 Multistage Polyphase Structure with Half-Band Filtering..
2.2 Spread-Reduction Scheme
2.3 Coefficient-Sharing Techniques
3. Circuit Design
3.1 lst-Stage
3.2 2nd- and 3rd-Stage
3.3 Digital Clock Phase Generation
4. Circuit Layout
5. Simulation Results
5.1 BehavioraI Simulations
5.2 Circuit-Level Simulations
6. Summary
6 DESIGN OF A 320 MHZ FREQUENCY-TRANSLATED SC BANDPASS INTERPOLATING FILTER
1. Introduction
2. Prototype System-Level Design
2.1 Multi-notch FIR Transfer Function
2.2 Time-Interleaved Serial ADB Polyphase Structure with
A utozeroing
3. Prototype Circuit-Level Design
3.1 Autozeroing ADB and Accumulator
3.2 High-Speed Multiplexer
3.3 Overall SC Circuit Architecture
3.4 Telescopic opamp with Wide-Swing Biasing
3.5 nMOS Switches 136
3.6 Noise Calculation
3.7 I/0 Circuitry
3.8 Low Timing-Skew Clock Generation
4. Layout Considerations
4.1 Device and Path Matching
4.2 Substrate and Supply Noise Decoupling
4.3 Shielding
4.4 Floor Plan
5. Simulation Results
5.1 Opamp Simulations
5.2 Filter Behavioral Simulations
5.3 Filter Transistor-Level and Post-Layout Simulations
6. Summary
7 EXPERIMENTAL RESULTS
1. Introduction
2. PCB Design
2.1 Floor Plan
2.2 Power Supplies and Decoupling
2.3 Biasing Currents
2.4 Input and Output Network
3. Measurement Setup and Results
3.1 Frequency Response
3.2 Time-Domain Signal Waveforms
3.3 One-Tone Signal Spectrum
3.4 Two-Tone Intermodulation Distortion
3.5 THD and IM3 vs. Input Signal Level
3.6 Noise Performance
3.7 CMRR and PSRR
4. Summary
8 CONCLUSIONS
APPENDIX 1 TIMING-MISMATCH ERRORS WITH NONUNIFORMLY HOLDING EFFECTS
1. Spectrum Expressions for IU-ON(SH) and IN-CON(SH)
1.1 IU-ON(SH)
1.2 IN-CON(SH)
2. Closed Form SINAD Expression for IU-ON(SH) and IN-CON(SH)
2.1 IU-ON(SH)
2.2 IN-CON(SH)
3. Closed Form SFDR Expression for IN-CON(SH) systems
4. Spectrum Correlation of IN-OU(IS) and IU-ON(SH)
APPENDIX 2 NOISE ANALYSIS FOR SC ADB DELAY LINE AND POLYPHASE SUBFILTERS
1. Output Noise of ADB Delay Line
2. Output Noise of Polyphase Subfilters
2.1 Using TSI Input Coefficient SC Branches
2.2 Using OFR Input Coefficient SC Branches
APPENDIX 3 GAIN, PHASE AND OFFSET ERRORS FOR GOC MF SC DELAY CIRCUIT I AND J
1. GOC MF SC Delay Circuit I
2. GOC MF SC Delay Circuit J
