梁宇華

研究方向

1、混合信號積體電路設計；

2、基於新型器件的模擬電路研究。

學術論文：

A 9.1ENOB 200MS/s Asynchronous SAR ADC With Hybrid Single-Ended/Differential DAC in 55-nm CMOS for Image Sensing Signals.IEEE Sensors Journal.2018,18(17)
A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-mu m CMOS for Medical Implant Devices.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS.2015,62(9)
A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-μm CMOS.IEEE Transactions on Circuits and Systems II.2019,66(1)
Utilization of Negative Capacitance FETs to Boost Analog Circuit Performances.IEEE Transactions on Very Large Scale Integration,accept.
Influence of Body Effect on Sample-and-Hold Circuit Design Using Negative Capacitance FET [J]. IEEE Transactions on Electron Device.IEEE Transactions on Electron Device.2018,65(9)
Analysis of DIBL Effect and Negative Resistance Performance for NCFET Based on a Compact SPICE Model [J]. IEEE Transactions on Electron Device.IEEE Transactions on Electron Device.2018,65(12)

專利：