李華偉(中國科學院計算技術研究所研究員)

李華偉，博士，中科院計算所研究員、博士生導師，中國計算機學會容錯計算專業委員會主任，中國計算機學會理事。

基本介紹

• 中文名：李華偉
• 國籍：中國
• 民族：漢族
• 職業：研究員
• 畢業院校：湘潭大學，中國科學院計算技術研究所
• 主要成就：2003年度中國科學院傑出科技成就獎2012年度國家技術發明獎二等獎

學習及工作經歷

1992年9月-1996年7月 湘潭大學，計算機科學與技術專業，本科畢業；

1996年9月-1999年7月 中國科學院計算技術研究所，計算機套用技術專業，碩士畢業；

1999年9月-2001年7月 中國科學院計算技術研究所，計算機套用技術專業，博士畢業；

2001年7月至今，就職於中國科學院計算技術研究所，現為計算機體系結構國家重點實驗室研究員、博士生導師。

國內外學術任職情況

2016-01-01-今,中國計算機學會容錯計算專委會, 主任

2016-01-01-今,中國計算機學會, 理事

2014-12-31-2018-12-31,IEEE TVLSI期刊編委, Associate Editor

2014-01-01-今,《計算機研究與發展》編委

2010-01-01-今,《計算機輔助設計與圖形學學報》編委,

2007-12-30-2015-12-31,中國計算機學會容錯專業委員會, 秘書長

現研究內容及主要工作

主要從事VLSI測試、可靠設計、驗證、容錯計算領域的套用基礎研究工作。主持的主要國家項目如下：

1、國家自然科學基金重點項目，差錯容忍計算器件基礎理論與方法，2015/01-2019/12。

2、國家自然科學基金面上項目，考慮積體電路時延變異性的矽後定時驗證方法，2012/01-2015/12。

3、國家自然科學基金面上項目，避免過度測試的時延測試方法，2008/01-2010/12。

4、國家重點基礎研究發展計畫（973計畫）項目，高性能處理晶片的設計驗證與測試，2005/12–2010/12。

5、國家高技術研究發展計畫（863計畫）項目，可信計算平台軟硬體系統安全測試評估模型、測試方法以及測試自動化技術，2007/07–2009/12。

6、國家自然科學基金面上項目，面向串擾的時延測試，2007/01-2009/12。

主要科研成果及獲獎情況

獲獎情況

1、成果“星載微處理器系統驗證-測試-恢復技術及套用”榮獲2012年度國家技術發明獎二等獎。

2、成果“32位星載容錯控制計算機系統關鍵技術及套用”榮獲2014年度北京市科學技術獎一等獎。

3、成果“高性能處理晶片的測試和可靠性設計關鍵技術”榮獲2011年度中國質量協會質量技術獎一等獎。

4、成果“積體電路邏輯測試與驗證基礎技術”榮獲2007年度北京市科學技術獎三等獎。

5、成果“數字電路實速檢測和故障診斷技術及其套用”榮獲2008年度北京市科學技術獎三等獎。

6、作為“龍芯CPU”研究集體成員，榮獲2003年度中科院傑出科技成就獎（榮譽）。

代表性學術論文

[1] Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li, “Retention-Aware DRAM Assembly and Repair for Future FGR Memories”, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 36, No.5, pp.705-718, 2017.

[2] Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, and Sandip Kundu, “Abstraction-Guided Simulation Using Markov Analysis for Functional Verification,” IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No.2, pp.285-297, 2016.

[3] Yanhong Zhou, Tiancheng Wang, Huawei Li, Tao Lv, Xiaowei Li, “Functional Test Generation for Hard-to-reach States Using Path Constraint Solving,” IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No.6, pp.999-1011, 2016.

[4] Guihai Yan, Faqiang Sun, Huawei Li, Xiaowei Li, “CoreRank: Redeeming Imperfect Silicon by Dynamically Quantifying Core-level Healthy Condition of Manycore Processors”, IEEE Transactions on Computers, Vol. 65, No.3, pp.716-729, 2016.

[5] Yun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li, “Flip-flop Clustering based Trace Signal Selection for Post-Silicon Debug,” Proc. of IEEE VLSI Test Symposium (VTS’17), Paper 3A-2, USA, April 2017.

[6] Ying Wang, Huawei Li, Xiaowei Li, “Re-architecting the On-chip memory Sub-system of Machine-Learning Accelerator for Embedded Devices,” Prof. of IEEE International Conference On Computer Aided Design, USA, Nov. 2016.

[7] Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li, “DeepBurning: Automatic Generation of FPGA-based Learning Accelerators for the Neural Network Family”, IEEE/ACM Proceedings of Design, Automation Conference (DAC), USA, 2016.

[8] Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li, “DISCO: A Low Overhead In-Network Data Compressor for Energy-Efficient Chip Multi-Processors”, IEEE/ACM Proceedings of Design, Automation Conference (DAC), USA, 2016.

[9] Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li and Bo Liu, “An accurate algorithm for computing mutation coverage in model checking,” Prof. IEEE International Test Conference, USA, Paper 16.2, Nov. 2016.

[10] Yanhong Zhou, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li, “Path Constraint Solving based Test Generation for Observability-enhanced Branch Coverage,”, Proc. of IEEE VLSI Test Symposium (VTS’16), Paper 1B-2, USA, April 2016.

[11] Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li, “PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3D Die-Stacked PCM”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol.24, No.5, pp.1613-1625, 2016.

[12] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Data Remapping for Static NUCA in Degradable Chip Multiprocessors”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.5, pp. 879-892, 2015.

[13] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Economizing TSV resources in 3D Network-on-Chip design”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.3, pp. 493-506, 2015.

[14] Dawen Xu, Huawei Li, Amirali Ghofrani, K.-T. Cheng, Yinhe Han, Xiaowei Li, “Test-Quality Optimization for Variable n-Detections of Transition Faults,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.8, pp. 1738-1749, August 2014.

[15] Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li, “ZoneDefense: A Fault-Tolerant Routing for 2D Meshes Without Virtual Channels,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.1, pp.113-126, 2014.

[16] Yuntan Fang, Huawei Li, and Xiaowei Li, “Lifetime enhancement techniques for PCM-based image buffer in multimedia applications,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.6, pp. 1450-1455, June 2014.

[17] Song Jin, Yinhe Han, Huawei Li, Xiaowei Li, “Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.5, May 2013, pp.821-833.

[18] Ying Zhang, Huawei Li, Xiaowei Li, “Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1220-1233.

[19] Zijian He, Tao Lv, Huawei Li, Xiaowei Li, “Test Path Selection for Capturing Delay Failures Under Statistical Timing Model,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1210-1219.

[20] Yuntan Fang, Huawei Li, Xiaowei Li, “RSAK: Random Stream AttacK for Phase Change Memory in Video Applications,” Proc. of IEEE VLSI Test Symposium (VTS’13), Paper 10B-3, Berkeley, CA, USA, May 2013.

[21] Xiang Fu, Huawei Li, Xiaowei Li, “Testable path selection and grouping for faster than at-speed testing,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.2, 2012, pp.236-247.

[22] Songwei Pei, Huawei Li, Xiaowei Li, “Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.12, 2012, pp. 2157-2169.

[23] Songwei Pei, Huawei Li, Xiaowei Li, “A High-Precision On-Chip Path Delay Measurement Architecture,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.9, 2012, pp.1565-1577.

[24] Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li, “Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.10, 2011, pp.1787-1800.

[25] Minjin Zhang, Huawei Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling Effects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.11, 2011, pp.1969-1982.

[26] Songwei Pei, Huawei Li, and Xiaowei Li, “A Unified Test Architecture for on-Line and Off-Line Delay Fault Detections", Proc. IEEE VLSI Test Symposium (VTS’11), 2011, pp.272-277.

[27] Huawei Li, Dawen Xu, K.-T. Cheng, “GPU-accelerated fault simulation and its new applications,” Proc. 2011 International Symposium on VLSI Design, Automation and Test (V LSI-DAT), invited paper in Special Session I (GPU Applications), Taiwan, April 2011.

[28] Huawei Li, Dawen Xu, Yinhe Han, K.-T. Cheng, Xiaowei Li, “nGFSIM: A GPU-Based 1-to-n-Detection Fault Simulator and its Applications,” Proc. IEEE 41st International Test Conference (ITC’10), Paper 12.1, Austin, USA, Oct. 2010.

[29] Zijian He, Tao Lv, Huawei Li, Xiaowei Li, “Fast path selection for testing of small delay defects considering path correlations,” Proc. of IEEE 28th VLSI Test Symposium (VTS’10), Santa Cruz, USA, May 2010, pp.3-8.

[30] Songwei Pei, Huawei Li, Xiaowei Li, “An On-Chip Clock Generation Scheme for Faster than-at-Speed Delay Testing”, Proc. of Design Automation and Test in Europe (DATE’10), France, Mar. 2010, pp.1353-1356.

[31] Huawei Li, Peifu Shen, and Xiaowei Li, “Robust Test Generation for Crosstalk-Induced Path Delay Faults,” 24th IEEE VLSI Test Symposium (VTS’06), Berkeley, CA, USA, May 2006.

[32] Huawei Li, and Xiaowei Li, “Selection of Crosstalk-induced Faults in Enhanced Delay Test,” Journal of Electronic Testing: Theory and Applications, Vol. 21, No.2, 2005, pp.181-195.

[33] Huawei Li, Yue Zhang, and Xiaowei Li, “Delay Test Pattern Generation Considering Crosstalk-induced Effects,” IEEE 12th Asian Test Symposium (ATS’03), Xi’an, China, Nov. 2003, pp.178-183.

[34] Huawei Li, Zhongcheng Li, and Yinghua Min, “Reduction of Number of Paths to be tested in Delay Testing,” Journal of Electronic Testing: Theory and Applications, Vol.16, No.5, Oct. 2000, pp. 477-485.

研究方向

積體電路設計自動化、近似計算、容錯計算、設計驗證與測試

所屬部門： 計算機體系結構國家重點實驗室

專家類別： 正高

其他備註：

博導，計算機系統結構