《微電子電路設計（第四版）（英文版）》是2011年1月電子工業出版社出版的圖書，作者是【美】Richard Jaeger（理察·耶格）、 Travis Blalock（特拉維斯·布萊洛克）。
基本介紹
- 中文名：微電子電路設計（第四版）（英文版）
- 作者：【美】Richard Jaeger（理察.耶格）、Travis Blalock（特拉維斯.布萊洛克）
- 出版時間：2011年1月
- 出版社：電子工業出版社
- 頁數：1360 頁
- ISBN：9787121127120
- 定價：132 元
- 開本：16 開
內容簡介,圖書目錄,
內容簡介
本書涵蓋了微電子電路設計所需基礎知識，主要由三個部分組成。第一部分介紹固態電子學與器件，討論了電子學的發展與電路分析方法和微電子器件的工作原理、I-V特性及SPICE模型等。第二部分為數字電路，包括數字電路的基本概念和CMOS電路、存儲電路、ECL與TTL等雙極型邏輯電路以及BiCMOS電路。第三部分為模擬電路，以理想運算放大器和SPICE仿真為基礎介紹了不同結構運算放大器的相關特性、小信號模型、具體分析方法和集成設計技術，最後討論了放大器的頻率回響、反饋和振盪器等問題。
通過學習本書可以了解現代微電子電路設計，包括模擬與數字，分立與集成，了解內部結構也有利於系統設計中對積體電路的適當選擇。
讀者對象：本書適用作電子與信息類各專業本科生基礎課的雙語教材或參考書，也可作為相關領域工程技術人員的參考資料。
圖書目錄
CONTENTS
Preface xx
PART ONE
SOLID STATE ELECTRONIC AND DEVICES 1
CHAPTER 1 INTRODUCTION TO ELECTRONICS 3
1.1A Brief History of Electronics:
From Vacuum Tubes to Giga-Scale
Integration 5
1.2Classification of Electronic Signals 8
1.2.1Digital Signals 9
1.2.2Analog Signals 9
1.2.3A/D and D/A Converters—Bridging the Analog and Digital Domains 10
1.3Notational Conventions 12
1.4Problem-Solving Approach 13
1.5Important Concepts from Circuit Theory 15
1.5.1Voltage and Current Division 15
1.5.2Th′
evenin and Norton Circuit Representations 16
1.6Frequency Spectrum of Electronic
Signals 21
1.7Amplifiers 22
1.7.1Ideal Operational Amplifiers 23
1.7.2Amplifier Frequency Response 25
1.8 Element Variations in Circuit Design 26
1.8.1Mathematical Modeling of Tolerances 26
1.8.2Worst-Case Analysis 27
1.8.3Monte Carlo Analysis 29
1.8.4Temperature Coefficients 32
1.9Numeric Precision 34
Summary 34
Key Terms 35
References 36
Additional Reading 36
Problems 37
CHAPTER 2 SOLID-STATE ELECTRONICS 42
2.1Solid-State Electronic Materials 44
2.2Covalent Bond Model 45
2.3Drift Currents and Mobility in
Semiconductors 48
2.3.1Drift Currents 48
2.3.2Mobility 49
2.3.3Velocity Saturation 49
2.4Resistivity of Intrinsic Silicon 50
2.5Impurities in Semiconductors 51
2.5.1Donor Impurities in Silicon 52
2.5.2Acceptor Impurities in Silicon 52
2.6Electron and Hole Concentrations in Doped
Semiconductors 52
2.6.1n-Type Material (ND＞NA ) 53
2.6.2p-Type Material (NA＞ND ) 54
2.7Mobility and Resistivity in Doped
Semiconductors 55
2.8Diffusion Currents 59
2.9Total Current 60
2.10Energy Band Model 61
2.10.1Electron–Hole Pair Generation in an Intrinsic Semiconductor 61
2.10.2Energy Band Model for a Doped Semiconductor 62
2.10.3Compensated Semiconductors 62
2.11Overview of Integrated Circuit
Fabrication 64
Summary 67
Key Terms 68
Reference 69
Additional Reading 69
Important Equations 69
Problems 70
CHAPTER 3 SOLID-STATE DIODES AND DIODE CIRCUITS 74
3.1The pn Junction Diode 75
3.1.1pn Junction Electrostatics 75
3.1.2Internal Diode Currents 79
viii Contents
3.2The i-v Characteristics of the Diode 80 3.14 Full-Wave Rectifier Circuits 123
3.3The Diode Equation: A Mathematical Model 3.14.1 Full-Wave Rectifier with Negative
for the Diode 82 Output Voltage 124
3.4Diode Characteristics Under Reverse, Zero, 3.15 Full-Wave Bridge Rectification 125
and Forward Bias 85 3.16 Rectifier Comparison and Design
3.4.1Reverse Bias 85 Tradeoffs 125
3.4.2Zero Bias 85 3.17 Dynamic Switching Behavior of the
3.4.3Forward Bias 86 Diode 129
3.5Diode Temperature Coefficient 89 3.18 Photo Diodes, Solar Cells, and
3.6Diodes Under Reverse Bias 89 Light-Emitting Diodes 130
3.6.1Saturation Current in Real 3.18.1 Photo Diodes and
Diodes 90 Photodetectors 130
3.6.2Reverse Breakdown 91 3.18.2 Power Generation from Solar
3.6.3Diode Model for the Breakdown Cells 131 Region 92 3.18.3 Light-Emitting Diodes (LEDs) 132
3.7pn Junction Capacitance 92 Summary 133
3.7.1Reverse Bias 92 Key Terms 134
3.7.2Forward Bias 93 Reference 135
3.8Schottky Barrier Diode 93 Additional Reading 135
3.9Diode SPICE Model and Layout 94 Problems 135
3.10Diode Circuit Analysis 96
3.10.1Load-Line Analysis 96 CHAPTER 4
3.10.2Analysis Using the Mathematical
FIELD-EFFECT TRANSISTORS 145
Model for the Diode 98
3.10.3The Ideal Diode Model 102 4.1 Characteristics of the MOS Capacitor 146
3.10.4Constant Voltage Drop Model 104 4.1.1 Accumulation Region 147
3.10.5Model Comparison and 4.1.2 Depletion Region 148 Discussion 105 4.1.3 Inversion Region 148
3.11Multiple-Diode Circuits 106 4.2 The NMOS Transistor 148
3.12Analysis of Diodes Operating in the 4.2.1 Qualitative i -v Behavior of the Breakdown Region 109 NMOS Transistor 149
3.12.1Load-Line Analysis 109 4.2.2 Triode Region Characteristics of the
3.12.2Analysis with the Piecewise Linear NMOS Transistor 150 Model 109 4.2.3 On Resistance 153
3.12.3Voltage Regulation 110 4.2.4 Saturation of the i -v
3.12.4Analysis Including Zener Characteristics 154 Resistance 111 4.2.5 Mathematical Model in the
3.12.5Line and Load Regulation 112 Saturation (Pinch-Off) Region 155
3.13Half-Wave Rectifier Circuits 113 4.2.6 Transconductance 157
3.13.1Half-Wave Rectifier with Resistor 4.2.7 Channel-Length Modulation 157 Load 113 4.2.8 Transfer Characteristics and
3.13.2Rectifier Filter Capacitor 114 Depletion-Mode MOSFETS 158
3.13.3Half-Wave Rectifier with RC 4.2.9 Body Effect or Substrate Load 115 Sensitivity 159
3.13.4Ripple Voltage and Conduction 4.3 PMOS Transistors 161
Interval 116 4.4 MOSFET Circuit Symbols 163
3.13.5Diode Current 118 4.5 Capacitances in MOS Transistors 165
3.13.6Surge Current 120 4.5.1 NMOS Transistor Capacitances in
3.13.7Peak-Inverse-Voltage (PIV) the Triode Region 165 Rating 120 4.5.2 Capacitances in the Saturation
3.13.8Diode Power Dissipation 120 Region 166
3.13.9Half-Wave Rectifier with Negative 4.5.3 Capacitances in Cutoff 166 Output Voltage 121 4.6 MOSFET Modeling in SPICE 167
Contents ix
4.7MOS Transistor Scaling 169
4.7.1Drain Current 169
4.7.2Gate Capacitance 169
4.7.3Circuit and Power Densities 170
4.7.4Power-Delay Product 170
4.7.5Cutoff Frequency 171
4.7.6High Field Limitations 171
4.7.7Subthreshold Conduction 172
4.8MOS Transistor Fabrication and Layout Design Rules 172
4.8.1Minimum Feature Size and Alignment Tolerance 173
4.8.2MOS Transistor Layout 173
4.9Biasing the NMOS Field-Effect
Transistor 176
4.9.1Why Do We Need Bias? 176
4.9.2Constant Gate-Source Voltage Bias 178
4.9.3Load Line Analysis for the Q-Point 181
4.9.4Four-Resistor Biasing 182
4.10Biasing the PMOS Field-Effect
Transistor 188
4.11The Junction Field-Effect Transistor
(JFET) 190
4.11.1The JFET with Bias Applied 191
4.11.2JFET Channel with Drain-Source Bias 191
4.11.3n-Channel JFET i -v Characteristics 193
4.11.4The p-Channel JFET 195
4.11.5Circuit Symbols and JFET Model Summary 195
4.11.6JFET Capacitances 196
4.12JFET Modeling in SPICE 197
4.13Biasing the JFET and Depletion-Mode
MOSFET 198
Summary 200
Key Terms 202
References 203
Problems 204
CHAPTER 5 BIPOLAR JUNCTION TRANSISTORS 217
5.1Physical Structure of the Bipolar
Transistor 218
5.2The Transport Model for the npn
Transistor 219
5.2.1Forward Characteristics 220
5.2.2Reverse Characteristics 222
5.2.3The Complete Transport Model Equations for Arbitrary Bias Conditions 223
5.3The pnp Transistor 225
5.4Equivalent Circuit Representations for the Transport Models 227
5.5The i-v Characteristics of the Bipolar
Transistor 228
5.5.1 Output Characteristics 228
5.5.2 Transfer Characteristics 229
5.6The Operating Regions of the Bipolar
Transistor 230
5.7Transport Model Simplifications 231
5.7.1Simplified Model for the Cutoff Region 231
5.7.2Model Simplifications for the Forward-Active Region 233
5.7.3Diodes in Bipolar Integrated Circuits 239
5.7.4Simplified Model for the Reverse-Active Region 240
5.7.5Modeling Operation in the Saturation Region 242
5.8Nonideal Behavior of the Bipolar
Transistor 245
5.8.1Junction Breakdown Voltages 246
5.8.2Minority-Carrier Transport in the Base Region 246
5.8.3Base Transit Time 247
5.8.4Diffusion Capacitance 249
5.8.5Frequency Dependence of the Common-Emitter Current Gain 250
5.8.6The Early Effect and Early Voltage 250
5.8.7Modeling the Early Effect 251
5.8.8Origin of the Early Effect 251
5.9Transconductance 252
5.10Bipolar Technology and SPICE Model 253
5.10.1 Qualitative Description 253
5.10.2 SPICE Model Equations 254
5.10.3 High-Performance Bipolar Transistors 255
5.11Practical Bias Circuits for the BJT 256
5.11.1Four-Resistor Bias Network 258
5.11.2Design Objectives for the Four-Resistor Bias Network 260
5.11.3Iterative Analysis of the Four-Resistor Bias Circuit 266
5.12Tolerances in Bias Circuits 266
5.12.1Worst-Case Analysis 267
5.12.2Monte Carlo Analysis 269
Summary 272
Key Terms 274
References 274
Problems 275
x
Contents
PART TWO6.11.1 Capacitances in Logic Circuits 337
6.11.2Dynamic Response of the NMOS
DIGITAL ELECTRONICS 285
Inverter with a Resistive Load 338
6.11.3Pseudo NMOS Inverter 343
CHAPTER 6
6.11.4 A Final Comparison of NMOS INTRODUCTION TO DIGITAL ELECTRONICS 287 Inverter Delays 344
6.11.5Scaling Based Upon Reference 6.1 Ideal Logic Gates 289 Circuit Simulation 3466.2 Logic Level Definitions and Noise
6.11.6Ring Oscillator Measurement of
Margins289 Intrinsic Gate Delay 346
6.2.1Logic Voltage Levels 291
6.11.7Unloaded Inverter Delay 347
6.2.2Noise Margins 291 6.12 PMOS Logic 349
6.2.3Logic Gate Design Goals 292
6.12.1PMOS Inverters 3496.3 Dynamic Response of Logic Gates 293
6.12.2NOR and NAND Gates 352
6.3.1Rise Time and Fall Time 293
Summary 352
6.3.2Propagation Delay 294
Key Terms 354
6.3.3Power-Delay Product 294
References 355
6.4 Review of Boolean Algebra 295
Additional Reading 355
6.5 NMOS Logic Design 297
Problems 355
6.5.1NMOS Inverter with Resistive
Load 298
CHAPTER 7
6.5.2Design of the W/L Ratio of MS 299
6.5.3Load Resistor Design 300 COMPLEMENTARY MOS (CMOS) LOGIC
6.5.4Load-Line Visualization 300 DESIGN 367
6.5.5On-Resistance of the Switching 7.1 CMOS Inverter Technology 368Device 302
7.1.1CMOS Inverter Layout 370
6.5.6Noise Margin Analysis 303 7.2 Static Characteristics of the CMOS
6.5.7Calculation of VIL and VOH 303
Inverter 370
6.5.8Calculation of VIH and VOL 304
7.2.1CMOS Voltage Transfer
6.5.9Load Resistor Problems 305 Characteristics 371
6.6 Transistor Alternatives to the Load
7.2.2Noise Margins for the CMOS
Resistor 306
Inverter 373
6.6.1The NMOS Saturated Load 7.3 Dynamic Behavior of the CMOS Inverter 375
Inverter307
7.3.1Propagation Delay Estimate 375
6.6.2NMOS Inverter with a Linear Load
7.3.2Rise and Fall Times 377Device 315
7.3.3Performance Scaling 377
6.6.3NMOS Inverter with a
7.3.4Delay of Cascaded Inverters 379Depletion-Mode Load 316 7.4 Power Dissipation and Power Delay Product
6.6.4Static Design of the Pseudo NMOS
in CMOS 380
Inverter319
7.4.1Static Power Dissipation 3806.7 NMOS Inverter Summary and
7.4.2Dynamic Power Dissipation 381Comparison 323
7.4.3Power-Delay Product 3826.8 NMOS NAND and NOR Gates 324 7.5 CMOS NOR and NAND Gates 384
6.8.1NOR Gates 325
7.5.1CMOS NOR Gate 384
6.8.2NAND Gates 326
7.5.2CMOS NAND Gates 387
6.8.3NOR and NAND Gate Layouts in 7.6 Design of Complex Gates in CMOS 388NMOS Depletion-Mode 7.7 Minimum Size Gate Design and
Technology 327 Performance 393
6.9 Complex NMOS Logic Design 328 7.8 Dynamic Domino CMOS Logic 3956.10 Power Dissipation 333 7.9 Cascade Buffers 397
6.10.1Static Power Dissipation 333
7.9.1Cascade Buffer Delay Model 397
6.10.2Dynamic Power Dissipation 334
7.9.2Optimum Number of Stages 398
6.10.3Power Scaling in MOS Logic 7.10 The CMOS Transmission Gate 400Gates 335 7.11 CMOS Latchup 4016.11 Dynamic Behavior of MOS Logic Gates 337
Contents xi
Summary 404 9.1.2 Current Switch Analysis for Key Terms 405 vI ＞ VREF 463 References 406 9.1.3 Current Switch Analysis for Problems 406 vI ＜VREF 464
9.2 The Emitter-Coupled Logic (ECL) Gate 464 CHAPTER 8 9.2.1 ECL Gate with vI = VH 465
9.2.2ECL Gate with vI = VL 466
MOS MEMORY AND STORAGE CIRCUITS 416
9.2.3Input Current of the ECL Gate 466
8.1Random Access Memory 417 9.2.4 ECL Summary 466
8.1.1Random Access Memory (RAM) 9.3 Noise Margin Analysis for the ECL Gate 467 Architecture 417 9.3.1 VIL , VOH , VIH , and VOL 467
8.1.2A 256-Mb Memory Chip 418 9.3.2 Noise Margins 468
8.2Static Memory Cells 419 9.4 Current Source Implementation 469
8.2.1Memory Cell Isolation and 9.5 The ECL OR-NOR Gate 471
Access—The 6-T Cell 422 9.6 The Emitter Follower 473
8.2.2The Read Operation 422 9.6.1 Emitter Follower with a Load
8.2.3Writing Data into the 6-T Cell 426 Resistor 474
8.3Dynamic Memory Cells 428 9.7 “Emitter Dotting’’ or “Wired-OR’’ Logic 476
8.3.1The One-Transistor Cell 430 9.7.1 Parallel Connection of
8.3.2Data Storage in the 1-T Cell 430 Emitter-Follower Outputs 477
8.3.3Reading Data from the 1-T Cell 431 9.7.2 The Wired-OR Logic Function 477
8.3.4The Four-Transistor Cell 433 9.8 ECL Power-Delay Characteristics 477
8.4Sense Amplifiers 434 9.8.1 Power Dissipation 477
8.4.1A Sense Amplifier for the 6-T 9.8.2 Gate Delay 479 Cell 434 9.8.3 Power-Delay Product 480
8.4.2A Sense Amplifier for the 1-T 9.9 Current Mode Logic 481 Cell 436 9.9.1 CML Logic Gates 481
8.4.3The Boosted Wordline Circuit 438 9.9.2 CML Logic Levels 482
8.4.4Clocked CMOS Sense 9.9.3 VEE Supply Voltage 482 Amplifiers 438 9.9.4 Higher-Level CML 483
8.5Address Decoders 440 9.9.5 CML Power Reduction 484
8.5.1NOR Decoder 440 9.9.6 NMOS CML 485
8.5.2NAND Decoder 440 9.10 The Saturating Bipolar Inverter 487
8.5.3Decoders in Domino CMOS 9.10.1 Static Inverter Characteristics 488 Logic 443 9.10.2 Saturation Voltage of the Bipolar
8.5.4Pass-Transistor Column Transistor 488 Decoder 443 9.10.3 Load-Line Visualization 491
8.6Read-Only Memory (ROM) 444 9.10.4 Switching Characteristics of the
8.7Flip-Flops 447 Saturated BJT 491
8.7.1RS Flip-Flop 449 9.11 A Transistor-Transistor Logic (TTL)
8.7.2The D-Latch Using Transmission Prototype 494 Gates 450 9.11.1 TTL Inverter for vI = VL 494
8.7.3 A Master-Slave D Flip-Flop 450 9.11.2 TTL Inverter for vI = VH 495 Summary 451 9.11.3 Power in the Prototype TTL Key Terms 452 Gate 496 References 452 9.11.4 VIH , VIL, and Noise Margins for the Problems 453 TTL Prototype 496
9.11.5Prototype Inverter Summary 498
9.11.6Fanout Limitations of the TTL
CHAPTER 9
Prototype 498
BIPOLAR LOGIC CIRCUITS 460
9.12 The Standard 7400 Series TTL Inverter 500
9.1The Current Switch (Emitter-Coupled 9.12.1 Analysis for vI = VL 500
Pair) 461 9.12.2 Analysis for vI = VH 501
9.1.1Mathematical Model for Static
Behavior of the Current Switch 462
xii Contents
9.12.3Power Consumption 503
9.12.4TTL Propagation Delay and Power-Delay Product 503
9.12.5TTL Voltage Transfer Characteristic and Noise Margins 503
9.12.6Fanout Limitations of Standard TTL 504
9.13Logic Functions in TTL 504
9.13.1Multi-Emitter Input Transistors 505
9.13.2TTL NAND Gates 505
9.13.3Input Clamping Diodes 506
9.14Schottky-Clamped TTL 506
9.15Comparison of the Power-Delay Products of
ECL and TTL 508
9.16BiCMOS Logic 508
9.16.1BiCMOS Buffers 509
9.16.2BiNMOS Inverters 511
9.16.3BiCMOS Logic Gates 513
Summary 513
Key Terms 515
References 515
Additional Reading 515
Problems 516
PART THREE
ANALOG ELECTRONICS 527
CHAPTER 10 ANALOG SYSTEMS AND IDEAL OPERATIONAL AMPLIFIERS 529
10.1An Example of an Analog Electronic
System 530
10.2Amplification 531
10.2.1Voltage Gain 532
10.2.2Current Gain 533
10.2.3Power Gain 533
10.2.4The Decibel Scale 534
10.3Two-Port Models for Amplifiers 537
10.3.1The g-parameters 537
10.4Mismatched Source and Load
Resistances 541
10.5Introduction to Operational Amplifiers 544
10.5.1The Differential Amplifier 544
10.5.2Differential Amplifier Voltage Transfer Characteristic 545
10.5.3Voltage Gain 545
10.6Distortion in Amplifiers 548
10.7Differential Amplifier Model 549
10.8Ideal Differential and Operational
Amplifiers 551
10.8.1Assumptions for Ideal Operational Amplifier Analysis 551
10.9Analysis of Circuits Containing Ideal
Operational Amplifiers 552
10.9.1The Inverting Amplifier 553
10.9.2The Transresistance Amplifier—A Current-to-Voltage Converter 556
10.9.3The Noninverting Amplifier 558
10.9.4The Unity-Gain Buffer, or Voltage Follower 561
10.9.5The Summing Amplifier 563
10.9.6The Difference Amplifier 565
10.10Frequency-Dependent Feedback 568
10.10.1Bode Plots 568
10.10.2The Low-Pass Amplifier 568
10.10.3The High-Pass Amplifier 572
10.10.4Band-Pass Amplifiers 575
10.10.5An Active Low-Pass Filter 578
10.10.6An Active High-Pass Filter 581
10.10.7The Integrator 582
10.10.8The Differentiator 586
Summary 586
Key Terms 588
References 588
Additional Reading 589
Problems 589
CHAPTER 11 NONIDEAL OPERATIONAL AMPLIFIERS AND FEEDBACK AMPLIFIER STABILITY 600
11.1Classic Feedback Systems 601
11.1.1Closed-Loop Gain Analysis 602
11.1.2Gain Error 602
11.2Analysis of Circuits Containing Nonideal
Operational Amplifiers 603
11.2.1Finite Open-Loop Gain 603
11.2.2Nonzero Output Resistance 606
11.2.3Finite Input Resistance 610
11.2.4Summary of Nonideal Inverting and Noninverting Amplifiers 614
11.3Series and Shunt Feedback Circuits 615
11.3.1Feedback Amplifier Categories 615
11.3.2Voltage Amplifiers—Series-Shunt Feedback 616
11.3.3Transimpedance Amplifiers—Shunt-Shunt Feedback 616
11.3.4Current Amplifiers—Shunt-Series Feedback 616
11.3.5Transconductance Amplifiers—Series-Series Feedback 616
11.4Unified Approach to Feedback Amplifier Gain Calculation 616
Contents xiii
11.4.1Closed-Loop Gain Analysis 617 11.12.5 An Alternate Interpretation of
11.4.2Resistance Calculation Using CMRR 657 Blackman’S Theorem 617 11.12.6 Power Supply Rejection Ratio 657
11.5Series-Shunt Feedback–Voltage 11.13 Frequency Response and Bandwidth of
Amplifiers 617 Operational Amplifiers 659
11.5.1Closed-Loop Gain Calculation 618 11.13.1 Frequency Response of the
11.5.2Input Resistance Calculation 618 Noninverting Amplifier 661
11.5.3Output Resistance 11.13.2 Inverting Amplifier Frequency Calculation 619 Response 664
11.5.4Series-Shunt Feedback Amplifier 11.13.3 Using Feedback to Control Summary 620 Frequency Response 666
11.6Shunt-Shunt Feedback—Transresistance 11.13.4 Large-Signal Limitations—Slew Amplifiers 624 Rate and Full-Power
11.6.1Closed-Loop Gain Calculation 625 Bandwidth 668
11.6.2Input Resistance Calculation 625 11.13.5 Macro Model for Operational
11.6.3Output Resistance Calculation 625 Amplifier Frequency Response 669
11.6.4Shunt-Shunt Feedback Amplifier 11.13.6 Complete Op Amp Macro Models in Summary 626 SPICE 670
11.7Series-Series Feedback—Transconductance 11.13.7 Examples of Commercial
Amplifiers 629 General-Purpose Operational
11.7.1Closed-Loop Gain Calculation 630 Amplifiers 670
11.7.2Input Resistance Calculation 630 11.14 Stability of Feedback Amplifiers 671
11.7.3Output Resistance Calculation 631 11.14.1 The Nyquist Plot 671
11.7.4Series-Series Feedback Amplifier 11.14.2 First-Order Systems 672 Summary 631 11.14.3 Second-Order Systems and Phase
11.8Shunt-Series Feedback—Current Margin 673
Amplifiers 633 11.14.4 Step Response and Phase
11.8.1Closed-Loop Gain Calculation 634 Margin 674
11.8.2Input Resistance Calculation 635 11.14.5 Third-Order Systems and Gain
11.8.3Output Resistance Calculation 635 Margin 677
11.8.4Series-Series Feedback Amplifier 11.14.6 Determining Stability from the Summary 635 Bode Plot 678
11.9Finding the Loop Gain Using Successive Summary 682
Voltage and Current Injection 638 Key Terms 684
11.9.1Simplifications 641 References 684
11.10Distortion Reduction Through the Use of Problems 685 Feedback 641
11.11DC Error Sources and Output Range CHAPTER 12 Limitations 642
OPERATIONAL AMPLIFIER APPLICATIONS 697
11.11.1Input-Offset Voltage 643
11.11.2Offset-Voltage Adjustment 644 12.1 Cascaded Amplifiers 698
11.11.3Input-Bias and Offset 12.1.1 Two-Port Representations 698 Currents 645 12.1.2 Amplifier Terminology Review 700
11.11.4Output Voltage and Current 12.1.3 Frequency Response of Cascaded Limits 647 Amplifiers 703
11.12Common-Mode Rejection and Input 12.2 The Instrumentation Amplifier 711 Resistance 650 12.3 Active Filters 714
11.12.1Finite Common-Mode Rejection 12.3.1 Low-Pass Filter 714 Ratio 650 12.3.2 A High-Pass Filter with Gain 718
11.12.2Why Is CMRR Important? 651 12.3.3 Band-Pass Filter 720
11.12.3Voltage-Follower Gain Error Due to 12.3.4 The Tow-Thomas Biquad 722 CMRR 654 12.3.5 Sensitivity 726
11.12.4Common-Mode Input 12.3.6 Magnitude and Frequency Resistance 656 Scaling 727
xiv Contents
12.4Switched-Capacitor Circuits 728
12.4.1A Switched-Capacitor Integrator 728
12.4.2Noninverting SC Integrator 730
12.4.3Switched-Capacitor Filters 732
12.5Digital-to-Analog Conversion 733
12.5.1D/A Converter Fundamentals 733
12.5.2D/A Converter Errors 734
12.5.3Digital-to-Analog Converter Circuits 737
12.6Analog-to-Digital Conversion 740
12.6.1A/D Converter Fundamentals 741
12.6.2Analog-to-Digital Converter Errors 742
12.6.3Basic A/D Conversion Techniques 743
12.7Oscillators 754
12.7.1The Barkhausen Criteria for Oscillation 754
12.7.2Oscillators Employing Frequency-Selective RC Networks 755
12.8Nonlinear Circuit Applications 760
12.8.1A Precision Half-Wave Rectifier 760
12.8.2Nonsaturating Precision-Rectifier Circuit 761
12.9Circuits Using Positive Feedback 763
12.9.1The Comparator and Schmitt Trigger 763
12.9.2The Astable Multivibrator 765
12.9.3The Monostable Multivibrator or One Shot 766
Summary 770
Key Terms 772
Additional Reading 773
Problems 773
CHAPTER 13 SMALL-SIGNAL MODELING AND LINEAR AMPLIFICATION 786
13.1The Transistor as an Amplifier 787
13.1.1The BJT Amplifier 788
13.1.2The MOSFET Amplifier 789
13.2Coupling and Bypass Capacitors 790
13.3Circuit Analysis Using dc and ac Equivalent
Circuits 792
13.3.1 Menu for dc and ac Analysis 792
13.4Introduction to Small-Signal Modeling 796
13.4.1Graphical Interpretation of the Small-Signal Behavior of the Diode 796
13.4.2Small-Signal Modeling of the Diode 797
13.5Small-Signal Models for Bipolar Junction
Transistors 799
13.5.1 The Hybrid-Pi Model 801
13.5.2 Graphical Interpretation of the Transconductance 802
13.5.3Small-Signal Current Gain 802
13.5.4The Intrinsic Voltage Gain of the BJT 803
13.5.5Equivalent Forms of the Small-Signal Model 804
13.5.6Simplified Hybrid Pi Model 805
13.5.7Definition of a Small Signal for the Bipolar Transistor 805
13.5.8Small-Signal Model for the pnp Transistor 807
13.5.9ac Analysis Versus Transient Analysis in SPICE 807
13.6The Common-Emitter (C-E) Amplifier 808
13.6.1Terminal Voltage Gain 809
13.6.2Input Resistance 809
13.6.3Signal Source Voltage Gain 810
13.7Important Limits and Model
Simplifications 810
13.7.1A Design Guide for the Common-Emitter Amplifier 810
13.7.2Upper Bound on the Common-Emitter Gain 812
13.7.3Small-Signal Limit for the Common-emitter Amplifier 812
13.8Small-Signal Models for Field-Effect
Transistors 815
13.8.1Small-Signal Model for the MOSFET 815
13.8.2Intrinsic Voltage Gain of the MOSFET 817
13.8.3Definition of Small-Signal Operation for the MOSFET 817
13.8.4Body Effect in the Four-Terminal MOSFET 818
13.8.5Small-Signal Model for the PMOS Transistor 819
13.8.6Small-Signal Model for the Junction Field-Effect Transistor 820
13.9Summary and Comparison of the Small-Signal Models of the BJT and FET 821
13.10The Common-Source Amplifier 824
13.10.1Common-Source Terminal Voltage Gain 825
13.10.2Signal Source Voltage Gain for the Common-Source Amplifier 825
13.10.3A Design Guide for the Common-Source Amplifier 826
13.10.4Small-Signal Limit for the Common-Source Amplifier 827
Contents xv
13.10.5Input Resistances of the Common-Emitter and Common-Source Amplifiers 829
13.10.6Common-Emitter and Common-Source Output Resistances 832
13.10.7Comparison of the Three Amplifier Resistances 838
13.11Common-Emitter and Common-Source Amplifier Summary 838
13.11.1Guidelines for Neglecting the Transistor Output Resistance 839
13.12Amplifier Power and Signal Range 839
13.12.1Power Dissipation 839
13.12.2Signal Range 840
Summary 843
Key Terms 844
Problems 845
CHAPTER 14 SINGLE-TRANSISTOR AMPLIFIERS 857
14.1Amplifier Classification 858
14.1.1Signal Injection and Extraction—The BJT 858
14.1.2Signal Injection and Extraction—The FET 859
14.1.3Common-Emitter (C-E) and Common-Source (C-S) Amplifiers 860
14.1.4Common-Collector (C-C) and Common-Drain (C-D) Topologies 861
14.1.5Common-Base (C-B) and Common-Gate (C-G) Amplifiers 863
14.1.6Small-Signal Model Review 864
14.2Inverting Amplifiers—Common-Emitter and Common-Source Circuits 864
14.2.1The Common-Emitter (C-E) Amplifier 864
14.2.2Common-Emitter Example Comparison 877
14.2.3The Common-Source Amplifier 877
14.2.4Small-Signal Limit for the Common-Source Amplifier 880
14.2.5Common-Emitter and Common-Source Amplifier Characteristics 884
14.2.6C-E/C-S Amplifier Summary 885
14.2.7Equivalent Transistor Representation of the Generalized C-E/C-S Transistor 885
14.3Follower Circuits—Common-Collector and Common-Drain Amplifiers 886
14.3.1Terminal Voltage Gain 886
14.3.2Input Resistance 887
14.3.3Signal Source Voltage Gain 888
14.3.4Follower Signal Range 888
14.3.5Follower Output Resistance 889
14.3.6Current Gain 890
14.3.7C-C/C-D Amplifier Summary 890
14.4Noninverting Amplifiers—Common-Base and Common-Gate Circuits 894
14.4.1Terminal Voltage Gain and Input Resistance 895
14.4.2Signal Source Voltage Gain 896
14.4.3Input Signal Range 897
14.4.4Resistance at the Collector and Drain Terminals 897
14.4.5Current Gain 898
14.4.6Overall Input and Output Resistances for the Noninverting Amplifiers 899
14.4.7C-B/C-G Amplifier Summary 902
14.5Amplifier Prototype Review and Comparison 903
14.5.1The BJT Amplifiers 903
14.5.2The FET Amplifiers 905
14.6Common-Source Amplifiers Using MOS Inverters 907
14.6.1Voltage Gain Estimate 908
14.6.2Detailed Analysis 909
14.6.3Alternative Loads 910
14.6.4Input and Output Resistances 911
14.7Coupling and Bypass Capacitor Design 914
14.7.1Common-Emitter and Common-Source Amplifiers 914
14.7.2Common-Collector and Common-Drain Amplifiers 919
14.7.3Common-Base and Common-Gate Amplifiers 921
14.7.4Setting Lower Cutoff Frequency fL 924
14.8Amplifier Design Examples 925
14.8.1Monte Carlo Evaluation of the Common-Base Amplifier Design 934
14.9Multistage ac-Coupled Amplifiers 939
14.9.1A Three-Stage ac-Coupled Amplifier 939
14.9.2Voltage Gain 941
14.9.3Input Resistance 943
14.9.4Signal Source Voltage Gain 943
14.9.5Output Resistance 943
14.9.6Current and Power Gain 944
xvi Contents
14.9.7Input Signal Range 945
14.9.8Estimating the Lower Cutoff Frequency of the Multistage Amplifier 948
Summary 950
Key Terms 951
Additional Reading 952
Problems 952
CHAPTER 15 DIFFERENTIAL AMPLIFIERS AND OPERATIONAL AMPLIFIER DESIGN 968
15.1Differential Amplifiers 969
15.1.1Bipolar and MOS Differential Amplifiers 969
15.1.2dc Analysis of the Bipolar Differential Amplifier 970
15.1.3Transfer Characteristic for the Bipolar Differential Amplifier 972
15.1.4ac Analysis of the Bipolar Differential Amplifier 973
15.1.5Differential-Mode Gain and Input and Output Resistances 974
15.1.6Common-Mode Gain and Input Resistance 976
15.1.7Common-Mode Rejection Ratio (CMRR) 978
15.1.8Analysis Using Differential-and Common-Mode Half-Circuits 979
15.1.9Biasing with Electronic Current Sources 982
15.1.10Modeling the Electronic Current Source in SPICE 983
15.1.11dc Analysis of the MOSFET Differential Amplifier 983
15.1.12Differential-Mode Input
Signals 985
15.1.13Small-Signal Transfer Characteristic for the MOS Differential Amplifier 986
15.1.14Common-Mode Input Signals 986
15.1.15Two-Port Model for Differential Pairs 987
15.2Evolution to Basic Operational
Amplifiers 991
15.2.1A Two-Stage Prototype for an Operational Amplifier 992
15.2.2Improving the Op Amp Voltage Gain 997
15.2.3Output Resistance Reduction 998
15.2.4A CMOS Operational Amplifier Prototype 1002
15.2.5BiCMOS Amplifiers 1004
15.2.6All Transistor Implementations 1004
15.3Output Stages 1006
15.3.1The Source Follower—A Class-A Output Stage 1006
15.3.2Efficiency of Class-A Amplifiers 1007
15.3.3Class-B Push-Pull Output Stage 1008
15.3.4Class-AB Amplifiers 1010
15.3.5Class-AB Output Stages for Operational Amplifiers 1011
15.3.6Short-Circuit Protection 1011
15.3.7Transformer Coupling 1013
15.4Electronic Current Sources 1016
15.4.1Single-Transistor Current Sources 1017
15.4.2Figure of Merit for Current Sources 1017
15.4.3Higher Output Resistance Sources 1018
15.4.4Current Source Design Examples 1018
Summary 1027
Key Terms 1028
References 1029
Additional Reading 1029
Problems 1029
CHAPTER 16 ANALOG INTEGRATED CIRCUIT DESIGN TECHNIQUES 1046
16.1Circuit Element Matching 1047
16.2Current Mirrors 1049
16.2.1dc Analysis of the MOS Transistor Current Mirror 1049
16.2.2Changing the MOS Mirror Ratio 1051
16.2.3dc Analysis of the Bipolar Transistor Current Mirror 1052
16.2.4Altering the BJT Current Mirror Ratio 1054
16.2.5Multiple Current Sources 1055
16.2.6Buffered Current Mirror 1056
16.2.7Output Resistance of the Current Mirrors 1057
16.2.8Two-Port Model for the Current Mirror 1058
16.2.9The Widlar Current Source 1060
16.2.10The MOS Version of the Widlar Source 1063
Contents xvii
16.3High-Output-Resistance Current
Mirrors 1063
16.3.1The Wilson Current Sources 1064
16.3.2Output Resistance of the Wilson Source 1065
16.3.3Cascode Current Sources 1066
16.3.4Output Resistance of the Cascode Sources 1067
16.3.5Regulated Cascode Current Source 1068
16.3.6Current Mirror Summary 1069
16.4Reference Current Generation 1072
16.5Supply-Independent Biasing 1073
16.5.1A VBE -Based Reference 1073
16.5.2The Widlar Source 1073
16.5.3Power-Supply-Independent Bias Cell 1074
16.5.4A Supply-Independent MOS Reference Cell 1075
16.6The Bandgap Reference 1077
16.7The Current Mirror As an Active
Load 1081
16.7.1CMOS Differential Amplifier with Active Load 1081
16.7.2Bipolar Differential Amplifier with Active Load 1088
16.8Active Loads in Operational
Amplifiers 1092
16.8.1CMOS Op Amp Voltage Gain 1092
16.8.2dc Design Considerations 1093
16.8.3Bipolar Operational Amplifiers 1095
16.8.4Input Stage Breakdown 1096
16.9The A741 Operational Amplifier 1097
16.9.1Overall Circuit Operation 1097
16.9.2Bias Circuitry 1098
16.9.3dc Analysis of the 741 Input Stage 1099
16.9.4ac Analysis of the 741 Input Stage 1102
16.9.5Voltage Gain of the Complete Amplifier 1103
16.9.6The 741 Output Stage 1107
16.9.7Output Resistance 1109
16.9.8Short Circuit Protection 1109
16.9.9Summary of the A741 Operational Amplifier Characteristics 1109
16.10The Gilbert Analog Multiplier 1110 Summary 1112 Key Terms 1113 References 1114 Problems 1114
CHAPTER 17 AMPLIFIER FREQUENCY RESPONSE 1128
17.1Amplifier Frequency Response 1129
17.1.1Low-Frequency Response 1130
17.1.2Estimating ωL in the Absence of a Dominant Pole 1130
17.1.3High-Frequency Response 1133
17.1.4Estimating ωH in the Absence of a Dominant Pole 1133
17.2Direct Determination of the Low-Frequency Poles and Zeros—The Common-Source Amplifier 1134
17.3Estimation of ωL Using the Short-Circuit
Time-Constant Method 1139
17.3.1Estimate of ωL for the Common-Emitter Amplifier 1140
17.3.2Estimate of ωL for the Common-Source Amplifier 1144
17.3.3Estimate of ωL for the Common-Base Amplifier 1145
17.3.4Estimate of ωL for the Common-Gate Amplifier 1146
17.3.5Estimate of ωL for the Common-
