《計算機組織與結構：性能設計（第八版）（英文版）》是2012年7月電子工業出版社出版的圖書，作者是William Stallings （威廉 斯托林斯）。
基本介紹
- 書名：計算機組織與結構：性能設計（第八版）（英文版）
- 作者：William Stallings （威廉 斯托林斯）
- ISBN：9787121170607
- 頁數：796頁
- 定價：99元
- 出版社：電子工業出版社
- 出版時間：2012年7月
- 開本：16開
內容簡介,圖書目錄,
內容簡介
本書以Intel x86系列通用處理器和ARM系列嵌入式處理器作為主要考察實例，將當代計算機系統性能設計問題和計算機組織與結構的基本概念及原理緊密聯繫。首先介紹計算機的發展與演變，引入性能評價和性能設計的概念，然後以自頂而下的方式逐層展開介紹計算機系統、存儲器體系結構、I/O及互連、計算機算術、指令集體系結構的設計及其實現技術、控制器設計，最後還介紹了處理器的各種並行組織技術。本書特色在於探討和揭示面向性能的各種設計博弈和實現考量，追逐性能極大化的同時顧及系統整體的性能平衡。
圖書目錄
CONTENTS
Chapter 0 Reader’s Guide 1
0.1 Outline of the Book 2
0.2 A Roadmap for Readers and Instructors 2
0.3 Why Study Computer Organization and Architecture 3
0.4 Internet and Web Resources 4
PART ONE OVERVIEW 7
Chapter 1 Introduction 8
1.1 Organization and Architecture 9
1.2 Structure and Function 10
1.3 Key Terms and Review Questions 15
Chapter 2 Computer Evolution and Performance 16
2.1 A Brief History of Computers 17
2.2 Designing for Performance 38
2.3 The Evolution of the Intel x86 Architecture 44
2.4 Embedded Systems and the ARM 46
2.5 Performance Assessment 50
2.6 Recommended Reading and Web Sites 57
2.7 Key Terms, Review Questions, and Problems 59
PART TWO THE COMPUTER SYSTEM 63
Chapter 3 A Top-Level View of Computer Function and Interconnection 65
3.1 Computer Components 66
3.2 Computer Function 68
3.3 Interconnection Structures 83
3.4 Bus Interconnection 85
3.5 PCI 95
3.6 Recommended Reading and Web Sites 104
3.7 Key Terms, Review Questions, and Problems 104
Appendix 3A Timing Diagrams 108
Chapter 4 Cache Memory 110
4.1 Computer Memory System Overview 111
4.2 Cache Memory Principles 118
4.3 Elements of Cache Design 121
4.4 Pentium 4 Cache Organization 140
4.5 ARM Cache Organization 143
4.6 Recommended Reading 145
4.7 Key Terms, Review Questions, and Problems 146
Appendix 4A Performance Characteristics of Two-Level Memories 151
Chapter 5 Internal Memory Technology 158
5.1 Semiconductor Main Memory 159
5.2 Error Correction 169
5.3 Advanced DRAM Organization 173
5.4 Recommended Reading and Web Sites 179
5.5 Key Terms, Review Questions, and Problems 180
Chapter 6 External Memory 184
6.1 Magnetic Disk 185
6.2 RAID 194
6.3 Optical Memory 203
6.4 Magnetic Tape 210
6.5 Recommended Reading and Web Sites 212
6.6 Key Terms, Review Questions, and Problems 214
Chapter 7 Input/Output 217
7.1 External Devices 219
7.2 I/O Modules 222
7.3 Programmed I/O 224
7.4 Interrupt-Driven I/O 228
7.5 Direct Memory Access 236
7.6 I/O Channels and Processors 242
7.7 The External Interface: FireWire and Infiniband 244
7.8 Recommended Reading and Web Sites 253
7.9 Key Terms, Review Questions, and Problems 254
Chapter 8 Operating System Support 259
8.1 Operating System Overview 260
8.2 Scheduling 271
8.3 Memory Management 277
8.4 Pentium Memory Management 288
8.5 ARM Memory Management 293
8.6 Recommended Reading and Web Sites 298
8.7 Key Terms, Review Questions, and Problems 299
PART THREE THE CENTRAL PROCESSING UNIT 303
Chapter 9 Computer Arithmetic 305
9.1 The Arithmetic and Logic Unit (ALU) 306
9.2 Integer Representation 307
9.3 Integer Arithmetic 312
9.4 Floating-Point Representation 327
9.5 Floating-Point Arithmetic 334
9.6 Recommended Reading and Web Sites 342
9.7 Key Terms, Review Questions, and Problems 344
Chapter 10 Instruction Sets: Characteristics and Functions 348
10.1 Machine Instruction Characteristics 349
10.2 Types of Operands 356
10.3 Intel x86 and ARM Data Types 358
10.4 Types of Operations 362
10.5 Intel x86 and ARM Operation Types 374
10.6 Recommended Reading 384
10.7 Key Terms, Review Questions, and Problems 385
Appendix 10A Stacks 390
Appendix 10B Little, Big, and Bi-Endian 396
Chapter 11 Instruction Sets: Addressing Modes and Formats 400
11.1 Addressing 401
11.2 x86 and ARM Addressing Modes 408
11.3 Instruction Formats 413
11.4 x86 and ARM Instruction Formats 421
11.5 Assembly Language 426
11.6 Recommended Reading 428
11.7 Key Terms, Review Questions, and Problems 428
Chapter 12 Processor Structure and Function 432
12.1 Processor Organization 433
12.2 Register Organization 435
12.3 The Instruction Cycle 440
12.4 Instruction Pipelining 444
12.5 The x86 Processor Family 461
12.6 The ARM Processor 469
12.7 Recommended Reading 475
12.8 Key Terms, Review Questions, and Problems 476
Chapter 13 Reduced Instruction Set Computers (RISCs) 480
13.1 Instruction Execution Characteristics 482
13.2 The Use of a Large Register File 487
13.3 Compiler-Based Register Optimization 492
13.4 Reduced Instruction Set Architecture 494
13.5 RISC Pipelining 500
13.6 MIPS R4000 504
13.7 SPARC 511
13.8 The RISC versus CISC Controversy 517
13.9 Recommended Reading 518
13.10 Key Terms, Review Questions, and Problems 518
Chapter 14 Instruction-Level Parallelism and Superscalar Processors 522
14.1 Overview 524
14.2 Design Issues 528
14.3 Pentium 4 538
14.4 ARM Cortex-A8 544
14.5 Recommended Reading 552
14.6 Key Terms, Review Questions, and Problems 554
PART FOUR THE CONTROL UNIT 559
Chapter 15 Control Unit Operation 561
15.1 Micro-operations 563
15.2 Control of the Processor 569
15.3 Hardwired Implementation 581
15.4 Recommended Reading 584
15.5 Key Terms, Review Questions, and Problems 584
Chapter 16 Microprogrammed Control 586
16.1 Basic Concepts 587
16.2 Microinstruction Sequencing 596
16.3 Microinstruction Execution 602
16.4 TI 8800 614
16.5 Recommended Reading 624
16.6 Key Terms, Review Questions, and Problems 625
PART FIVE PARALLEL ORGANIZATION 627
Chapter 17 Parallel Processing 628
17.1 The Use of Multiple Processors 630
17.2 Symmetric Multiprocessors 632
17.3 Cache Coherence and the MESI Protocol 640
17.4 Multithreading and Chip Multiprocessors 646
17.5 Clusters 653
17.6 Nonuniform Memory Access Computers 660
17.7 Vector Computation 664
17.8 Recommended Reading and Web Sites 676
17.9 Key Terms, Review Questions, and Problems 677
Chapter 18 Multicore Computers 684
18.1 HardwarePerformance Issues 685
18.2 Software Performance Issues 690
18.3 Multicore Organization 694
18.4 Intel x86 Multicore Organization 696
18.5 ARM11 MPCore 699
18.6 Recommended Reading and Web Sites 704
18.7 Key Terms, Review Questions, and Problems 705
Appendix A Projects for Teaching Computer Organization
and Architecture 707
A.1 Interactive Simulations 708
A.2 Research Projects 708
A.3 Simulation Projects 710
A.4 Assembly Language Projects 711
A.5 Reading/Report Assignments 711
A.6 Writing Assignments 712
A.7 Test Bank 712
Appendix B Assembly Language and Related Topics 713
B.1 Assembly Language 714
B.2 Assemblers 723
B.3 Loading and Linking 728
B.4 Recommended Reading and Web Sites 735
B.5 Key Terms, Review Questions, and Problems 736
ONLINE CHAPTERS
Chapter 19 Number Systems 19-1
19.1 The Decimal System 19-2
19.2 The Binary System 19-2
19.3 Converting between Binary and Decimal 19-3
19.4 Hexadecimal Notation 19-5
19.5 Key Terms, Review Questions, and Problems 19-8
Chapter 20 Digital Logic 20-1
20.1 Boolean Algebra 20-2
20.2 Gates 20-4
20.3 Combinational Circuits 20-7
20.4 Sequential Circuits 20-24
20.5 Programmable Logic Devices 20-33
20.6 Recommended Reading and Web Site 20-38
20.7 Key Terms and Problems 20-39
Chapter 21 The IA-64 Architecture 21-1
21.1 Motivation 21-3
21.2 General Organization 21-4
21.3 Predication, Speculation, and Software Pipelining 21-6
21.4 IA-64 Instruction Set Architecture 21-23
21.5 Itanium Organization 21-28
21.6 Recommended Reading and Web Sites 21-31
21.7 Key Terms, Review Questions, and Problems 21-32
ONLINE APPENDICES
Appendix C Hash Tables
Appendix D Victim Cache Strategies
D.1 Victim Cache
D.2 Selective Victim Cache
Appendix E Interleaved Memory
Appendix F International Reference Alphabet
Appendix G Virtual Memory Page Replacement Algorithms
Appendix H Recursive Procedures
H.1 Recursion
H.2 Activation Tree Representation
H.3 Stack Processing
H.4 Recursion and Iteration
Appendix I Additional Instruction Pipeline Topics
I.1 Pipeline Reservation Tables
I.2 Reorder Buffers
I.3 Scoreboarding
I.4 Tomasulo’s Algorithm
Appendix J Linear Tape Open Technology
Appendix K DDR SDRAM
Glossary 740
References 750
Index 763
