盧繼武

盧繼武,男,漢族,博士,湖南大學電氣與信息工程學院副教授,博士生導師

基本介紹

  • 中文名:盧繼武
  • 畢業院校:荷蘭特溫特大學
  • 學位/學歷:博士
  • 專業方向:電氣與信息工程
  • 任職院校:湖南大學
人物經歷,教育經歷,工作經歷,講授課程,研究方向,科研成果,學術成果,

人物經歷

教育經歷

2006.09 – 2011.06 荷蘭特溫特大學(Twente University) 電子工程博士
2002.09 – 2006.06 德國錫根大學(Siegen University) 物理碩士
1997.09 – 2001.06 浙江大學物理系 本科

工作經歷

2019-至今 博士生導師
2011-2014 美國國家技術與標準局 (NIST)客座研究員
2015年-至今 任湖南省電工學會 委員
2011年-至今 任IEEE電子器件協會 會員
國際電氣電子工程師學會 (IEEE)會員
Advances in Condensed Matter Physics 客座編輯
Journal of Solid State Electronics 審稿人
Journal of Semiconductor Manufacturing 審稿人

講授課程

電磁兼容原理,數字電子技術基礎,超高頻快速電路的信號完整性(計畫中)
半導體器件基礎

研究方向

第三代SiC功率半導體器件製備與仿真
微能源採掘系統
VLSI積體電路設計
超快速電路的設計與測試及其相關信號完整性問題

科研成果

1. 2007–2011,荷蘭STW基金(等同於中國的“863”計畫) 參與
2. 2011-2014,美國國家標準與技術院重點研究項目,主持2項,參與1項
3. 2015-2019,湖南大學青年教師成長計畫項目,主持
4. 2015-2017,中芯國際“02”國家重大專項產學研子課題,主持
5. 2019-至今,梯次利用動力電池套用場景分析及再利用壽命和經濟評估技術研究,主持

學術成果

1. J. Liu, M. Shi, J. Lu*, and M. P. Anantram, "Analysis of electrical-field-dependent Dzyaloshinskii-Moriya interaction and magnetocrystalline anisotropy in a two-dimensional ferromagnetic monolayer," Physical Review B, vol. 97, p. 054416, 02/16/ 2018
2. J. Liu, M. P. Anantram, X. Xu, and J. Lu, "Analysis of Sub-threshold Electron Transport Properties of Ultra-scaled Amorphous Phase Change Material Germanium Tellurid," in 2017 IEEE 12th International Conference on ASIC, Guiyang, 2017, p. Paper_ID 0919.
3. J. B. Sun and J. W. Lu*, "Interface Engineering and Gate Dielectric Engineering for High Performance Ge MOSFETs," Advances in Condensed Matter Physics, p. 9, 2015.
4. J. W. Lu#, G. F. JiaoE, J. P. Campbell, J. T. Ryan, K. P. Cheung, C. D. Young, Bersuker, G, Circuit speed timing jitter increase in random logic operation after NBTI stress, IEEE International Reliability Physics Symposium, 2014, USA,Hawaii, 2014.06
5. PBTI-Induced Random Timing Jitter in Circuit-Speed Random Logic; IEEE Transaction on Electron Device; 2014 volume 61, issue 11,pages 3613-3618; J. Lu, G. F. Jiao, C. Vaz, J.P. Campbell, J.T. Ryan, K. P. Cheung, G. Bersuker, C.D. Young; SCI 收錄
6. Device-Level Experimental Observations of NBTI-Induced Random Timing Jitter, IEEE Transaction on Device and Materials Reliability; 2014, volume 14, issue 4, pages 972-977; J. Lu#, G. F. Jiao#, J.P. Campbell, J.T. Ryan, K. P. Cheung, C.D. Young ,G. Bersuker, #co-first author, SCI收錄
7. Device Level PBTI-induced Timing Jitter Increase in Circuit-Speed Random Logic; IEEE International VLSI Technology Symposium; 2014, June 9-12, USA, Honolulu, HI, USA; J. Lu, C. Vaz, J.P. Campbell, J.T. Ryan, K. P. Cheung, G. F. Jiao, G. Bersuker, C.D. Young,EI收錄,電子器件領域最好的兩個國際會議之一
8. Circuit Speed Timing Jitter Increase in Random Logic Operation after NBTI Stress; IEEE International Reliability Physics Symposium; 2014 June 1-5, Waikoloa, HI, USA;J. Lu#, G. F. Jiao#, J.P. Campbell, J.T. Ryan, K. P. Cheung, C.D. Young ,G. Bersuker, #co-first author,EI 收錄
9. Impact of BTI on random logic circuit critical timing; 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT); 2014 Oct. 28-31,Guilin, China;K. P. Cheung, J. Lu, G. F. Jiao, C. Vaz,J.P. Campbell, J.T. Ryan, EI 收錄
10. Integration of solar cells on top of CMOS chips Part II: CIGS Solar cells; IEEE Transaction on Electron Device; 2011, volume 58, issue 8, pages 2620-2027; J. Lu, W. Liu, A. Y. Kovalgin, Y. Sun and J. Schmitz, SCI 收錄
11. Integration of solar cells on top of CMOS chips Part I: a-Si Solar cells; IEEE Transaction on Electron Device; 2011, volume 58, issue7, pages 2014-2021;J. Lu, C. H. M. Van Der Werf, A. Y. Kovalgin, R. E. I. Schropp, and J. Schmitz, SCI 收錄
12. Above-CMOS a-Si and CIGS solar cells for powering autonomous microsystems; 2010 IEEE International Electron Devices Meeting; 2010 Dec. 6-8,San Francisco, CA, USA,J. Lu, W. Liu, C.H.M. van der Werf, A.Y. Kovalgin, Y. Sun, R.E.I. Schropp, J. Schmitz,EI 收錄,電子器件領域最好的兩個國際會議之一
13. Materials Characterization of CIGS solar cells on Top of CMOS chips; 2011 MRS Spring Meeting; 2011 Apr. 25-29, San Francisco, CA,USA, 1325;J. Lu, W. Liu, A. Y. Kovalgin, Y. Sun and J. Schmitz,EI 收錄
14. Lu, J., A. Y. Kovalgin and J. Schmitz (2009). Influence of passivation process on chip performance. 12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2009, Technology Foundation (STW)

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