基本介紹
- 中文名：作業系統設計與實現（第3版）
- 作者：Andrew S. Tanenbaum
- 出版時間：2008年5月4日
- 出版社：清華大學出版社
- ISBN：9787302172765
- 定價：69 元
- 裝幀：平裝
圖書簡介,圖書目錄,
圖書簡介
本書是著名作者Andrew S. Tanenbaum關於作業系統的權威教材。
多數作業系統的教材只重理論而輕實踐，本書力圖實現這兩者之間的平衡。本書首先詳細探討了作業系統的基本原理，如進程、進程間通信、信號量、訊息傳遞、調度算法、輸入/輸出、死鎖、設備驅動程式、存儲管理、調頁算法、檔案系統設計、安全和保護機制等，然後詳細討論了一個具體的作業系統MINIX3的實現，並給出了該系統的完整原始碼，以便於讀者仔細研究。這樣不僅可以讓讀者掌握作業系統的基本原理，而且可讓讀者明白這些基本原理如何套用到實際作業系統設計中去，從而提供讀者的實際設計和實現能力。
本書可以作為高等院校計算機及相關專業“作業系統”的雙語教材，對程式開發人員、工程技術人員、系統架構師等專業人員也具有很高的參考價值。
圖書目錄
1 INTRODUCTION 1
1.1 WHAT IS AN OPERATING SYSTEM? 4
1.1.1 The Operating System as an Extended Machine 4
1.1.2 The Operating System as a Resource Manager 5
1.2 HISTORY OF OPERATING SYSTEMS 6
1.2.1 The First Generation (1945-55) Vacuum Tubes and Plugboards 7
1.2.2 The Second Generation (1955-65) Transistors and Batch Systems 7
1.2.3 The Third Generation (1965-1980)ICs and Multiprogramming 9
1.2.4 The Fourth Generation (1980-Present) Personal Computers 13
1.2.5 History of MINIX3 14
1.3 OPERATING SYSTEM CONCEPTS 17
1.3.1 Processes 18
1.3.2 Files20
1.3.3 The Shell 231.4 SYSTEM CALLS 24
1.4.1 System Calls for Process Management 25
1.4.2 System Calls for Signaling 29
1.4.3 System Calls for File Management 31
1.4.4 System Calls for Directory Management 36
1.4.5 System Calls for Protection 38
1.4.6 System Calls for Time Management 40
1.5 OPERATING SYSTEM STRUCTURE 40
1.5.1 Monolithic Systems 40
1.5.2 Layered Systems 43
1.5.3 Virtual Machines 44
1.5.4 Exokernels 47
1.5.5 Client-Server Model 47
1.6 OUTLINE OF THE REST OF THIS BOOK49
1.7SUMMARY49
2PROCESSES53
2.1 INTRODUCTION TO PROCESSES 53
2.1.1 The Process Model 54
2.1.2 Process Creation 55
2.1.3 Process Termination 57
2.1.4 Process Hierarchies 58
2.1.5 Process States 58
2.1.6 Implementation of Processes 60
2.1.7 Threads 62
2.2 INTERPROCESS COMMUNICATION
2.2.1 Race Conditions 67
2.2.2 Critical Sections 68
2.2.3 Mutual Exclusion with Busy Waiting 69
2.2.4 Sleep and Wakeup 74
2.2.5 Semaphores 76
2.2.6 Mutexes79
2.2.7 Monitors 79
2.2.8 Message Passing 83
2.3CLASSICALIPCPROBLEMS86
2.3.1TheDiningroiIOSOpIIersProbICm87
2.3.2TheReadersandWritersPI.oblelll90
24SCHEDULING91
2.4.1 Introduction to Scheduling 92
2.4.2 Scheduling in Batch Systems 97
2.4.3 Scheduling in Interactive Systems 100
2.4.4 Scheduling in Real-Time Systems107
2.4.5 Policy versus Mechanism 108
2.4.6 Thread Scheduling 108
2.5 OVERVIEW OF PROCESSES IN MINIX 3 110
2.5.1 The Internal Structure of MINIX 3110
2.5.2 Process Management in MINIX 3114
2.5.3 Interprocess Communication in MINIX 3 118
2.5.4 Process Scheduling in MINIX 3120
2.6 IMPLEMENTATION OF PROCESSES IN MINIX 3123
2.6.1 Organization of the MINIX 3 Source Code 123
2.6.2 Compiling and Runniing MINIX 3126
2.6.3 The Common Header Files128
2.6.4 The MINIX 3 Header Files 136
2.6.5 Process Data Structures and Header Files 144
2.6.6 Bootstrapping MINIX 3154
2.6.7 System Initialization 158
2.6.8 Interrupt Handling in MINIX 3165
2.6.9 Interprocess Communication in MINIX 3176
2.6.10 Scheduling in MINIX 3180
2.6.11 Hardware-Dependent Kernel Support 183
2.6.12 Utilities and the Kernel Library 188
2.7 THE SYSTEM TASK IN MINIX 3190
2.7.1 Overview of the System Task 192
2.7.2 Implementation of the System Task 195
2.7.3 Implementation of the System Libarary 198
2.9 THE CLOCK TASK IN MINIX 3 202
2.8.1 Clock Hardware 202
2.8.2 Clock Software 204
2.8.3 Overview of the Clock Driver in MINIX 3206
2.8.4 Implementation of the Clock Driver in MINIX 3 210
2.9 SUMMARY212
3INPUTIOUTPUT219
3.1 PRINCIPLES OF I/O HARDWARE220
3.1.1 1/O Devices 221
3.1.2 Device Controllers221
3.1.3 Memory-Mapped lO 223
3.1.4 Interrupts224
3.1.5 Direct Memory Access 225
3.2 PRINCIPLES OF vO SOFTWARE227
3.2.1 Goals of the l/O Software 227
3.2.2 Interrupt Handlers 229
3.2.3 Device Drivers 220
3.2.4 Device-Independent 1/O Software 231
3.2.5 User-Space io Software 234
3.3 DEADLOCKS235
3.3.1 Resources 236
3.3.2 Principles of Dcadlock 237
3.3.3 The Ostrich Algorithm 240
3.3.4 Detection and Recovery242
3.3.5 Deadlock Prevention 243
3.3.6 Deadlock Avoidance 245
3.4 OVERVIEW OF IO IN MINIX 3250
3.4.1 Interrupt Handlers in MINIX 3250
3.4.2 Device Drivers in MINIX 3254
3.4.3 Device-Independent vO Software in MINIX 3 257
3.4.4 User-level lO Software in MINIX 3258
3.4.5 Deadlock Handling in MINIX 3258
3.5 BLOCK DEVICES IN MINIX 3259
3.5.1 Overview of Block Device Drivers in MINIX 3260
3.5.2 Common Block Device Driver Software 263
3.5.3 The Driver Library 267
3.6 RAM DISKS269
3.6.1 RAM Disk Hardware and Software 269
3.6.2 Overview of the RAM Disk Driver in MINIX 3271
3.6.3 Implementation of the RAM Disk Driver in MINIX 3272
3.7 DISKS 276
3.7.1 Disk Hardware 276
3.7.2 RAID278
3.7.3 Disk Software 279
3.7.4 Overview of the Hard Disk Driver in MINIX 3285
3.7.5 Implementation of the Hard Disk Driver in MINIX 3288
3.7.6 Floppy Disk Handling 298
3.8 TERMINALS300
3.8.1 Terminal Hardware 301
3.8.2 Terminal Software 305
3.8.3 Overview of the Terminal Driver in MINIX 3 314
3.8.4 Implementation of the Device-Independent Terminal Driver 329
3.8.5 Implementation of the Keyboard Driver 348
3.8.6 Implementation of the Display Driver 355
3.9 SUMMARY 364
4 MEMORY MANAGEMENT 371
4.1 BASIC MEMORY MANAGEMENT372
4.1.1 Monoprogramming without Swapping or Paging 372
4.1.2 Multiprogramming with Fixed Partitions 373
4.1.3 Relocation and Protection 375
4.2 SWAPPING376
4.2.1 Memory Management with Bitmaps378
4.2.2 Memory Management with Linked Lists 379
4.3 VIRTUALMEMORY381
4.3.1 Paging 382
4.3.2 Page Tables386
4.3.3 TLBs—Translation Lookaside Buffers 390
4.3.4 Inverted Page Tables 393
4.4 PAGE REPLACEMENT ALGORITHMS394
4.4.1 The Optimal Page Replacement Algorithm 395
4.4.2 The Not Recently Used Page Replacement Algorithm 396
4.4.3 The First-In, First-Out (FIFO) Page Replacement Algorithm 397
4.4.4 The Second Chance Page Replacement Algorithm 397
4.4.5 The Clock Page Replacement Algorithm 398
4.4.6 The Least Recently Used (LRU) Page Replacement Algorithm 399
4.4.7 Simulating LRU in Software 399
4.5 DESIGN ISSUES FOR PAGING SYSTEMS 402
4.5.1 The Working Set Model 402
4.5.2 Local versus Global Allocation Policies 404
4.5.3 Page Size 406
4.5.4 Virtual Memory Interface 408
4.6 SEGMENTATION 408
4.6.1 Implementation of Pure Segmentation 412
4.6.2 Segmentation with Paging: The Intel Pentium 413
